/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos5433-bus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 compatible = "samsung,exynos-bus"; 13 clock-names = "bus"; 14 operating-points-v2 = <&bus_g2d_400_opp_table>; 19 compatible = "samsung,exynos-bus"; 21 clock-names = "bus"; 22 operating-points-v2 = <&bus_g2d_266_opp_table>; 27 compatible = "samsung,exynos-bus"; 29 clock-names = "bus"; 30 operating-points-v2 = <&bus_gscl_opp_table>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/opp/ |
H A D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
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H A D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Technologies, Inc. NVMEM OPP 10 - Ilia Lin <ilia.lin@kernel.org> 13 - $ref: opp-v2-base.yaml# 17 the CPU frequencies subset and voltage value of each OPP varies based on 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). [all …]
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H A D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Nishanth Menon <nm@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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H A D | opp-v2-qcom-level.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm OPP 10 - Niklas Cassel <nks@flawful.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2-qcom-level 20 '^opp-?[0-9]+$': 25 opp-level: true [all …]
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3399-op1-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 cluster0_opp: opp-table-0 { 8 compatible = "operating-points-v2"; 9 opp-shared; 12 opp-hz = /bits/ 64 <408000000>; 13 opp-microvolt = <800000>; 14 clock-latency-ns = <40000>; 17 opp-hz = /bits/ 64 <600000000>; 18 opp-microvolt = <825000>; [all …]
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H A D | rk3399-t-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 8 cluster0_opp: opp-table-0 { 9 compatible = "operating-points-v2"; 10 opp-shared; 13 opp-hz = /bits/ 64 <408000000>; 14 opp-microvolt = <875000 875000 1250000>; 15 clock-latency-ns = <40000>; 18 opp-hz = /bits/ 64 <600000000>; 19 opp-microvolt = <875000 875000 1250000>; [all …]
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H A D | rk3399-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 cluster0_opp: opp-table-0 { 8 compatible = "operating-points-v2"; 9 opp-shared; 12 opp-hz = /bits/ 64 <408000000>; 13 opp-microvolt = <825000 825000 1250000>; 14 clock-latency-ns = <40000>; 17 opp-hz = /bits/ 64 <600000000>; 18 opp-microvolt = <825000 825000 1250000>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3399-op1-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 cluster0_opp: opp-table0 { 8 compatible = "operating-points-v2"; 9 opp-shared; 12 opp-hz = /bits/ 64 <408000000>; 13 opp-microvolt = <800000>; 14 clock-latency-ns = <40000>; 17 opp-hz = /bits/ 64 <600000000>; 18 opp-microvolt = <825000>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. 6 - clock-names: Should contain the following: 7 "cpu" - The multiplexer for clock input of CPU cluster. 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock 11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for 13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml 15 - proc-supply: Regulator for Vproc of CPU cluster. 18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver 23 - mediatek,cci: 30 - #cooling-cells: [all …]
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H A D | qcom-cpufreq-nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ilia Lin <ilia.lin@kernel.org> 17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level 18 according to the required OPPs defined in the CPU OPP tables. 20 For old implementation efuses are parsed to select the correct opp table and 28 - qcom,apq8064 29 - qcom,apq8096 [all …]
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H A D | nvidia,tegra20-cpufreq.txt | 5 - clocks: Must contain an entry for the CPU clock. 6 See ../clocks/clock-bindings.txt for details. 7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details. 8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 10 For each opp entry in 'operating-points-v2' table: 11 - opp-supported-hw: Two bitfields indicating: 21 matches, the OPP gets enabled. 23 - opp-microvolt: CPU voltage triplet. 26 - cpu-supply: Phandle to the CPU power supply. 31 regulator-name = "vdd_cpu"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sdm660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 13 compatible = "qcom,adreno-512.0", "qcom,adreno"; 14 operating-points-v2 = <&gpu_sdm660_opp_table>; 16 gpu_sdm660_opp_table: opp-table { 17 compatible = "operating-points-v2"; 23 * at the same opp-level 25 opp-750000000 { 26 opp-hz = /bits/ 64 <750000000>; 27 opp-level = <RPM_SMD_LEVEL_TURBO>; 28 opp-peak-kBps = <5412000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5422-odroid-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source 6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. 10 #include <dt-bindings/clock/samsung,s2mps11.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 14 #include "exynos5422-cpus.dtsi" 27 stdout-path = "serial2:115200n8"; 31 compatible = "samsung,secure-firmware"; 35 fixed-rate-clocks { [all …]
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H A D | exynos4210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2010-2011 Linaro Ltd. 20 #include "exynos4-cpu-thermal.dtsi" 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-names = "bus"; 35 operating-points-v2 = <&bus_acp_opp_table>; 38 bus_acp_opp_table: opp-table { 39 compatible = "operating-points-v2"; [all …]
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H A D | exynos4x12.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 19 #include "exynos4-cpu-thermal.dtsi" 27 fimc-lite0 = &fimc_lite_0; 28 fimc-lite1 = &fimc_lite_1; 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-names = "bus"; 35 operating-points-v2 = <&bus_acp_opp_table>; 38 bus_acp_opp_table: opp-table { 39 compatible = "operating-points-v2"; [all …]
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H A D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 45 compatible = "arm,cortex-a9"; 48 clock-names = "cpu"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 55 compatible = "arm,cortex-a9"; 58 clock-names = "cpu"; [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra20-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1300000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1300000>; 15 opp-level = <1000000>; [all …]
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H A D | tegra30-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1350000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1350000>; 15 opp-level = <1000000>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/power/ |
H A D | qcom,rpmpd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <andersson@kernel.org> 19 - qcom,mdm9607-rpmpd 20 - qcom,msm8226-rpmpd 21 - qcom,msm8909-rpmpd 22 - qcom,msm8916-rpmpd 23 - qcom,msm8939-rpmpd 24 - qcom,msm8953-rpmpd [all …]
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/openbmc/linux/arch/arm/boot/dts/allwinner/ |
H A D | sun8i-r40-cpu-opp.dtsi | 2 cpu0_opp_table: opp-table-cpu { 3 compatible = "operating-points-v2"; 4 opp-shared; 6 opp-720000000 { 7 opp-hz = /bits/ 64 <720000000>; 8 opp-microvolt = <1000000 1000000 1300000>; 9 clock-latency-ns = <2000000>; 12 opp-912000000 { 13 opp-hz = /bits/ 64 <912000000>; 14 opp-microvolt = <1100000 1100000 1300000>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/allwinner/ |
H A D | sun50i-a64-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 cpu0_opp_table: opp-table-cpu { 8 compatible = "operating-points-v2"; 9 opp-shared; 11 opp-648000000 { 12 opp-hz = /bits/ 64 <648000000>; 13 opp-microvolt = <1040000>; 14 clock-latency-ns = <244144>; /* 8 32k periods */ 17 opp-816000000 { 18 opp-hz = /bits/ 64 <816000000>; [all …]
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H A D | sun50i-h5-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org> 5 cpu_opp_table: opp-table-cpu { 6 compatible = "operating-points-v2"; 7 opp-shared; 9 opp-408000000 { 10 opp-hz = /bits/ 64 <408000000>; 11 opp-microvolt = <1000000 1000000 1310000>; 12 clock-latency-ns = <244144>; /* 8 32k periods */ 15 opp-648000000 { [all …]
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H A D | sun50i-h6-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 cpu_opp_table: opp-table-cpu { 7 compatible = "allwinner,sun50i-h6-operating-points"; 8 nvmem-cells = <&cpu_speed_grade>; 9 opp-shared; 11 opp-480000000 { 12 clock-latency-ns = <244144>; /* 8 32k periods */ 13 opp-hz = /bits/ 64 <480000000>; 15 opp-microvolt-speed0 = <880000 880000 1200000>; 16 opp-microvolt-speed1 = <820000 820000 1200000>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/apple/ |
H A D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 11 #address-cells = <2>; 12 #size-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <0>; 18 cpu-map { 63 enable-method = "spin-table"; 64 cpu-release-addr = <0 0>; /* To be filled by loader */ 65 next-level-cache = <&l2_cache_0>; 66 i-cache-size = <0x20000>; [all …]
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