| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | exception_level.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Switch to non-secure mode
7 * This module contains the ARMv7 specific code required for leaving the
13 #include <asm/armv7.h>
18 * entry_non_secure() - entry point when switching to non-secure mode
20 * When switching to non-secure mode switch_to_non_secure_mode() calls this
29 debug("Reached non-secure mode\n"); in entry_non_secure()
36 * switch_to_non_secure_mode() - switch to non-secure mode
38 * Operating systems may expect to run in non-secure mode. Here we check if
39 * we are running in secure mode and switch to non-secure mode if necessary.
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| H A D | virt-v7.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Routines to transition ARMv7 processors from secure into non-secure state
7 * and from non-secure SVC into HYP mode
8 * needed to enable ARMv7 virtualization for current hypervisors
12 #include <asm/armv7.h>
41 return -1; in get_gicd_base_address()
55 size_t sz = __secure_end - __secure_start; in relocate_secure_section()
78 if (gic_dist_addr == -1) in smp_kick_all_cpus()
98 return -1; in armv7_init_nonsec()
103 * in SVC mode. Do not try to read it once in non-secure state, in armv7_init_nonsec()
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| H A D | nonsec_virt.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
11 #include <asm/armv7.h>
12 #include <asm/proc-armv/ptrace.h>
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
104 movs pc, lr @ ERET to non-secure
139 * of the non-secure and HYP mode transition. The GIC distributor specific
155 * Switch a core to non-secure state.
157 * 1. initialize the GIC per-core interface
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| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 17 bool "Broadcom BCM2837 SoC 32-bit support"
24 bool "Broadcom BCM2837 SoC 64-bit support"
39 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
41 support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
50 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
56 non-default option must be present in config.txt: enable_uart=1.
57 This is required for U-Boot to operate correctly, even if you only
60 This option creates a build targeting the ARMv7/AArch32 ISA.
66 Support for all BCM2836-based Raspberry Pi variants, such as
69 This option also supports BCM2837-based variants such as the RPi 3
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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| /openbmc/linux/arch/arm/mm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | cacheflush.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King
12 #include <asm/glue-cache.h>
17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
35 * See Documentation/core-api/cachetlb.rst for more information.
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
52 * inner shareable and invalidate the I-cache.
65 * - start - user start address (inclusive, page aligned)
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| /openbmc/linux/arch/arm/common/ |
| H A D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
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| H A D | kernel_mode_neon.rst | 6 -------------
10 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'
18 ------------
25 non-preemptible section for reasons outlined below.
29 -------------------------
50 ----------------------------
67 --------------------
69 like IEEE-754 compliant underflow handling etc. When the VFP unit needs such
80 ---------------------------------------
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
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| /openbmc/openbmc/poky/meta/classes-recipe/ |
| H A D | rust-common.bbclass | 4 # SPDX-License-Identifier: MIT
8 inherit rust-target-config
13 FILES:${PN}-dev += "${rustlibdir}/*.rlib ${rustlibdir}/*.rmeta"
14 FILES:${PN}-dbg += "${rustlibdir}/.debug"
16 RUSTLIB ?= "-L ${STAGING_DIR_HOST}${rustlibdir}"
17 RUST_DEBUG_REMAP = "--remap-path-prefix=${WORKDIR}=${TARGET_DBGSRC_DIR}"
19 RUSTLIB_DEP ??= "libstd-rs"
23 '''Determine if target is armv7'''
25 # in the case of *-native packages
50 # The llvm-target for armv7 is armv7-unknown-linux-gnueabihf
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/webkitgtk/ |
| H A D | webkitgtk3_2.44.3.bb | 4 (having javascriptcoregtk-4.1.pc instead of 6.0). \
9 LICENSE = "BSD-2-Clause & LGPL-2.0-or-later"
11 file://Source/WebCore/LICENSE-APPLE;md5=4646f90082c40bcf298c285f8bab0b12 \
12 file://Source/WebCore/LICENSE-LGPL-2;md5=36357ffde2b64ae177b2494445b79d21 \
13 file://Source/WebCore/LICENSE-LGPL-2.1;md5=a778a33ef338abbaf8b8a7c36b6eec80 \
16 SRC_URI = "https://www.webkitgtk.org/releases/webkitgtk-${PV}.tar.xz \
17 file://0001-FindGObjectIntrospection.cmake-prefix-variables-obta.patch \
19 file://no-musttail-arm.patch \
20 file://0001-LowLevelInterpreter.cpp-339-21-error-t6-was-not-decl.patch \
22 file://0001-Fix-build-issues-with-latest-Clang.patch \
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| /openbmc/openbmc/meta-raspberrypi/dynamic-layers/multimedia-layer/recipes-multimedia/rpidistro-vlc/files/ |
| H A D | 0007-armv6.patch | 1 Upstream-Status: Inappropriate
3 RPI-Distro repo forks original vlc and applies patches
6 --- a/modules/hw/mmal/blend_rgba_neon.S
8 @@ -1,10 +1,10 @@
9 - .syntax unified
10 - .arm
11 -// .thumb
12 - .text
15 .arch armv7-a
16 - .fpu neon-vfpv4
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
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| /openbmc/linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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| /openbmc/linux/tools/perf/util/ |
| H A D | cs-etm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
136 * table 6-12 Possible values for the TYPE field in an Exception instruction
137 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
192 * When working with per-thread scenarios the process under trace can
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | compat_alignment.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
29 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
58 offset.un = -offset.un; in do_alignment_finish_ldst()
64 regs->regs[RN_BITS(instr)] = addr; in do_alignment_finish_ldst()
75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd()
91 regs->regs[rd] = val; in do_alignment_ldrdstrd()
92 regs->regs[rd2] = val2; in do_alignment_ldrdstrd()
94 if (put_user(regs->regs[rd], (u32 __user *)addr) || in do_alignment_ldrdstrd()
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| /openbmc/u-boot/board/armltd/vexpress/ |
| H A D | vexpress_tc2.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/armv7.h>
11 #include <asm/u-boot.h>
27 * bit 12 = Use per-cpu mailboxes for power management in armv7_boot_nonsec_default()
28 * bit 13 = Power down the non-boot cluster in armv7_boot_nonsec_default()
30 * It is only when both of these are false that U-Boot's current in armv7_boot_nonsec_default()
43 const char *cci_compatible = "arm,cci-400-ctrl-if"; in ft_board_setup()
58 /* delete cci-control-port in each cpu node */ in ft_board_setup()
61 fdt_delprop(fdt, tmp, "cci-control-port"); in ft_board_setup()
67 prop = fdt_get_property(fdt, offset, "interface-type", in ft_board_setup()
[all …]
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | bootrom.c | 1 // SPDX-License-Identifier: GPL-2.0+
14 * Force the jmp_buf to the data-section, as .bss will not be valid
61 * All Rockchip BROM implementations enter with a valid stack-pointer,
63 * implementation both for ARMv7 and AArch64).
76 * brom_ctx: transfer back into the startup-code at in save_boot_params()
95 * A non-zero return value will instruct the BROM enter in save_boot_params()
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| /openbmc/u-boot/board/freescale/common/ |
| H A D | arm_sleep.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #error " Deep sleep needs non-secure mode support. "
13 #include <asm/armv7.h>
38 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) in is_warm_boot()
46 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; in fsl_dp_disable_console()
61 src = (u64 *)in_le32(&scfg->sparecr[2]); in dp_ddr_restore()
87 out_be32(&scfg->pmcintecr, 0); in ls1_psci_resume_fixup()
89 out_be32(&scfg->pmcintsr, 0xffffffff); in ls1_psci_resume_fixup()
92 tmp = in_be32(&scfg->dpslpcr); in ls1_psci_resume_fixup()
94 out_be32(&scfg->dpslpcr, tmp); in ls1_psci_resume_fixup()
[all …]
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| /openbmc/openbmc/poky/meta/recipes-sato/webkit/ |
| H A D | webkitgtk_2.46.5.bb | 5 LICENSE = "BSD-2-Clause & LGPL-2.0-or-later"
7 file://Source/WebCore/LICENSE-APPLE;md5=4646f90082c40bcf298c285f8bab0b12 \
8 file://Source/WebCore/LICENSE-LGPL-2;md5=36357ffde2b64ae177b2494445b79d21 \
9 file://Source/WebCore/LICENSE-LGPL-2.1;md5=a778a33ef338abbaf8b8a7c36b6eec80 \
12 SRC_URI = "https://www.webkitgtk.org/releases/${BPN}-${PV}.tar.xz \
13 file://0001-FindGObjectIntrospection.cmake-prefix-variables-obta.patch \
15 file://0001-CMake-Add-a-variable-to-control-macro-__PAS_ALWAYS_I.patch \
16 file://no-musttail-arm.patch \
17 file://t6-not-declared.patch \
18 file://0001-Support-ICU-76.1-build.patch \
[all …]
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| /openbmc/linux/drivers/iommu/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
29 bool "ARMv7/v8 Long Descriptor Format"
36 sizes at both stage-1 and stage-2, as well as address spaces
37 up to 48-bits in size.
43 Enable self-tests for LPAE page table allocator. This performs
44 a series of page-table consistency checks during boot.
49 bool "ARMv7/v8 Short Descriptor Format"
53 Enable support for the ARM Short-descriptor pagetable format.
54 This supports 32-bit virtual and physical addresses mapped using
[all …]
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/tbb/ |
| H A D | tbb_2021.13.0.bb | 1 DESCRIPTION = "Parallelism library for C++ - runtime files \
2 TBB is a library that helps you leverage multi-core processor \
4 higher-level, task-based parallelism that abstracts platform details \
6 HOMEPAGE = "https://software.intel.com/en-us/tbb"
7 LICENSE = "Apache-2.0"
10 DEPENDS:append:libc-musl = " libucontext"
11 DEPENDS:append:class-target = " hwloc"
17 SRC_URI = "git://github.com/oneapi-src/oneTBB.git;protocol=https;branch=${BRANCH} \
26 -DTBB_TEST=OFF \
27 -DCMAKE_BUILD_TYPE=Release \
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