1c061ce24SRob Herring# SPDX-License-Identifier: GPL-2.0 2c061ce24SRob Herring%YAML 1.2 3c061ce24SRob Herring--- 4c061ce24SRob Herring$id: http://devicetree.org/schemas/arm/pmu.yaml# 5c061ce24SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6c061ce24SRob Herring 7c061ce24SRob Herringtitle: ARM Performance Monitor Units 8c061ce24SRob Herring 9c061ce24SRob Herringmaintainers: 10c061ce24SRob Herring - Mark Rutland <mark.rutland@arm.com> 11c061ce24SRob Herring - Will Deacon <will.deacon@arm.com> 12c061ce24SRob Herring 13c061ce24SRob Herringdescription: |+ 14c061ce24SRob Herring ARM cores often have a PMU for counting cpu and cache events like cache misses 15c061ce24SRob Herring and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU 16c061ce24SRob Herring representation in the device tree should be done as under:- 17c061ce24SRob Herring 18c061ce24SRob Herringproperties: 19c061ce24SRob Herring compatible: 20c061ce24SRob Herring items: 21c061ce24SRob Herring - enum: 22c061ce24SRob Herring - apm,potenza-pmu 23640a3b7aSJanne Grunau - apple,avalanche-pmu 24640a3b7aSJanne Grunau - apple,blizzard-pmu 255a6bbd1dSMarc Zyngier - apple,firestorm-pmu 265a6bbd1dSMarc Zyngier - apple,icestorm-pmu 27a8e446e4SRobin Murphy - arm,armv8-pmuv3 # Only for s/w models 28c061ce24SRob Herring - arm,arm1136-pmu 29a8e446e4SRobin Murphy - arm,arm1176-pmu 30a8e446e4SRobin Murphy - arm,arm11mpcore-pmu 31a8e446e4SRobin Murphy - arm,cortex-a5-pmu 32a8e446e4SRobin Murphy - arm,cortex-a7-pmu 33a8e446e4SRobin Murphy - arm,cortex-a8-pmu 34a8e446e4SRobin Murphy - arm,cortex-a9-pmu 35a8e446e4SRobin Murphy - arm,cortex-a12-pmu 36a8e446e4SRobin Murphy - arm,cortex-a15-pmu 37a8e446e4SRobin Murphy - arm,cortex-a17-pmu 38a8e446e4SRobin Murphy - arm,cortex-a32-pmu 39a8e446e4SRobin Murphy - arm,cortex-a34-pmu 40a8e446e4SRobin Murphy - arm,cortex-a35-pmu 41a8e446e4SRobin Murphy - arm,cortex-a53-pmu 42a8e446e4SRobin Murphy - arm,cortex-a55-pmu 43a8e446e4SRobin Murphy - arm,cortex-a57-pmu 44a8e446e4SRobin Murphy - arm,cortex-a65-pmu 45a8e446e4SRobin Murphy - arm,cortex-a72-pmu 46a8e446e4SRobin Murphy - arm,cortex-a73-pmu 47a8e446e4SRobin Murphy - arm,cortex-a75-pmu 48a8e446e4SRobin Murphy - arm,cortex-a76-pmu 49a8e446e4SRobin Murphy - arm,cortex-a77-pmu 50750d43b4SSeiya Wang - arm,cortex-a78-pmu 5150eb8923SRobin Murphy - arm,cortex-a510-pmu 52*039768b5SRob Herring - arm,cortex-a520-pmu 5350eb8923SRobin Murphy - arm,cortex-a710-pmu 54*039768b5SRob Herring - arm,cortex-a715-pmu 55*039768b5SRob Herring - arm,cortex-a720-pmu 5650eb8923SRobin Murphy - arm,cortex-x1-pmu 5750eb8923SRobin Murphy - arm,cortex-x2-pmu 58*039768b5SRob Herring - arm,cortex-x3-pmu 59*039768b5SRob Herring - arm,cortex-x4-pmu 60a8e446e4SRobin Murphy - arm,neoverse-e1-pmu 61a8e446e4SRobin Murphy - arm,neoverse-n1-pmu 6250eb8923SRobin Murphy - arm,neoverse-n2-pmu 6350eb8923SRobin Murphy - arm,neoverse-v1-pmu 64c061ce24SRob Herring - brcm,vulcan-pmu 65c061ce24SRob Herring - cavium,thunder-pmu 66de3f6daaSThierry Reding - nvidia,denver-pmu 67de3f6daaSThierry Reding - nvidia,carmel-pmu 68a8e446e4SRobin Murphy - qcom,krait-pmu 69c061ce24SRob Herring - qcom,scorpion-pmu 70c061ce24SRob Herring - qcom,scorpion-mp-pmu 71c061ce24SRob Herring 72c061ce24SRob Herring interrupts: 73c061ce24SRob Herring # Don't know how many CPUs, so no constraints to specify 74c061ce24SRob Herring description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. 75c061ce24SRob Herring 76c061ce24SRob Herring interrupt-affinity: 77c061ce24SRob Herring $ref: /schemas/types.yaml#/definitions/phandle-array 7839bd2b6aSRob Herring items: 7939bd2b6aSRob Herring maxItems: 1 80c061ce24SRob Herring description: 81c061ce24SRob Herring When using SPIs, specifies a list of phandles to CPU 82c061ce24SRob Herring nodes corresponding directly to the affinity of 83c061ce24SRob Herring the SPIs listed in the interrupts property. 84c061ce24SRob Herring 85c061ce24SRob Herring When using a PPI, specifies a list of phandles to CPU 86c061ce24SRob Herring nodes corresponding to the set of CPUs which have 87c061ce24SRob Herring a PMU of this type signalling the PPI listed in the 88c061ce24SRob Herring interrupts property, unless this is already specified 89c061ce24SRob Herring by the PPI interrupt specifier itself (in which case 90c061ce24SRob Herring the interrupt-affinity property shouldn't be present). 91c061ce24SRob Herring 92c061ce24SRob Herring This property should be present when there is more than 93c061ce24SRob Herring a single SPI. 94c061ce24SRob Herring 95c061ce24SRob Herring qcom,no-pc-write: 96c061ce24SRob Herring type: boolean 97c061ce24SRob Herring description: 98c061ce24SRob Herring Indicates that this PMU doesn't support the 0xc and 0xd events. 99c061ce24SRob Herring 100c061ce24SRob Herring secure-reg-access: 101c061ce24SRob Herring type: boolean 102c061ce24SRob Herring description: 103c061ce24SRob Herring Indicates that the ARMv7 Secure Debug Enable Register 104c061ce24SRob Herring (SDER) is accessible. This will cause the driver to do 105c061ce24SRob Herring any setup required that is only possible in ARMv7 secure 106c061ce24SRob Herring state. If not present the ARMv7 SDER will not be touched, 107c061ce24SRob Herring which means the PMU may fail to operate unless external 108c061ce24SRob Herring code (bootloader or security monitor) has performed the 109c061ce24SRob Herring appropriate initialisation. Note that this property is 110c061ce24SRob Herring not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux 111c061ce24SRob Herring in Non-secure state. 112c061ce24SRob Herring 113c061ce24SRob Herringrequired: 114c061ce24SRob Herring - compatible 115c061ce24SRob Herring 1165be478f9SRob HerringadditionalProperties: false 1175be478f9SRob Herring 118c061ce24SRob Herring... 119