| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
63 /* programmable divider. 0 means fixed ratio to parent clock */
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
90 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
91 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
107 (div)->frac_width > 0)
109 #define selector_exists(sel) ((sel)->width != 0)
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
63 /* programmable divider. 0 means fixed ratio to parent clock */
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
90 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
91 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
107 (div)->frac_width > 0)
109 #define selector_exists(sel) ((sel)->width != 0)
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| /openbmc/linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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| H A D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
47 /* Divider and scaling helpers */
49 /* Convert a divider into the scaled divisor value it represents. */
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
56 * Build a scaled divider value as close as possible to the
68 combined <<= div->u.s.frac_width; in scaled_div_build()
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| H A D | clk-kona-setup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
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| /openbmc/linux/drivers/clk/ti/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
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| /openbmc/linux/drivers/media/i2c/cx25840/ |
| H A D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
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| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
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| /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | speed.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2004
15 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
20 uint sccr = in_be32(&immap->im_clkrst.car_sccr); in get_clocks()
21 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); in get_clocks() local
26 * (For example, the cogent CMA286-60 CPU module has no in get_clocks()
29 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; in get_clocks()
32 /* No Bus Divider active */ in get_clocks()
33 gd->bus_clk = gd->cpu_clk; in get_clocks()
36 gd->bus_clk = gd->cpu_clk / 2; in get_clocks()
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| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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| H A D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-divider-gate.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
66 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_bypass()
81 return &clkrst->crc_pll[clkid]; in get_pll()
100 return -1; in clock_ll_read_pll()
101 data = readl(&pll->pll_base); in clock_ll_read_pll()
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| /openbmc/linux/arch/powerpc/boot/ |
| H A D | cuboot-acadia.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for Acadia
23 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
27 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
36 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
37 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
38 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
39 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
25 * Note that no Tegra clock register actually uses all of bits 31:28 as
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
53 * @param divm input divider
54 * @param divn feedback divider
55 * @param divp post divider 2^n
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
80 * @param divm returns input divider
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| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_mvebu_a3700.c | 1 // SPDX-License-Identifier: GPL-2.0+
36 void __iomem *base = plat->base; in mvebu_serial_putc()
49 void __iomem *base = plat->base; in mvebu_serial_getc()
60 void __iomem *base = plat->base; in mvebu_serial_pending()
71 void __iomem *base = plat->base; in mvebu_serial_setbrg()
74 * Calculate divider in mvebu_serial_setbrg()
75 * baudrate = clock / 16 / divider in mvebu_serial_setbrg()
91 void __iomem *base = plat->base; in mvebu_serial_probe()
97 /* No Parity, 1 Stop */ in mvebu_serial_probe()
107 plat->base = devfdt_get_addr_ptr(dev); in mvebu_serial_ofdata_to_platdata()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-aspeed.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
40 * @flags: hardware-specific flags
59 * struct aspeed_reset - Aspeed reset controller
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| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
20 * DOC: basic adjustable divider clock that cannot gate
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | pc87360.rst | 12 Datasheets: No longer available
22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
33 Note that this parameter has no effect for the PC87360, PC87363 and PC87364
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_pll.c | 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
75 * @post_div: post divider
76 * @fb_div_max: feedback divider maximum
77 * @ref_div_max: reference divider maximum
78 * @fb_div: resulting feedback divider
79 * @ref_div: resulting reference divider
81 * Calculate feedback and reference divider for a given post divider. Makes
90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | conversion.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
29 #define DIVIDER 10000 macro
31 /* S2D13 value in [-3.00...0.9999] */
32 #define S2D13_MIN (-3 * DIVIDER)
33 #define S2D13_MAX (3 * DIVIDER)
49 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) in fixed_point_to_int_frac()
77 * convert_float_matrix - This converts a double into HW register spec defined format S2D13.
85 dc_fixpt_from_fraction(S2D13_MIN, DIVIDER); in convert_float_matrix()
87 dc_fixpt_from_fraction(S2D13_MAX, DIVIDER); in convert_float_matrix()
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| /openbmc/u-boot/drivers/i2c/ |
| H A D | fsl_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0
61 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
62 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
68 * The last entry of the table must have a value of {-1, X}, where X is same
69 * FDR/DFSR values as the second-to-last entry. This guarantees that any
72 * The values of the divider must be in increasing numerical order, i.e.
73 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
77 * Divider Ratio for SCL"
85 unsigned short divider; member
104 {-1, 31}
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