| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
21 - samsung,s3c6410-spi
22 - samsung,s5pv210-spi # for S5PV210 and S5PC110
23 - samsung,exynos4210-spi
24 - samsung,exynos5433-spi
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| /openbmc/linux/drivers/infiniband/hw/qib/ |
| H A D | qib_sd7220.c | 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
117 * Below keeps track of whether the "once per power-on" initialization has
120 * state of the reset "pin", is no longer valid. Instead, we check for the
126 struct qib_devdata *dd = ppd->dd; in qib_ibsd_ucode_loaded()
128 if (!dd->cspec->serdes_first_init_done && in qib_ibsd_ucode_loaded()
130 dd->cspec->serdes_first_init_done = 1; in qib_ibsd_ucode_loaded()
131 return dd->cspec->serdes_first_init_done; in qib_ibsd_ucode_loaded()
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| /openbmc/qemu/hw/hppa/ |
| H A D | machine.c | 3 * (C) Copyright 2018-2023 Helge Deller <deller@gmx.de>
13 #include "qemu/error-report.h"
20 #include "hw/char/serial-mm.h"
29 #include "hw/pci-host/astro.h"
30 #include "hw/pci-host/dino.h"
40 #define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
99 NULL, "isa-io", 0x800); in hppa_isa_bus()
125 return 0xe9; /* readback */ in io_cpu_read()
138 rtc_ref = val - time(NULL); in io_cpu_write()
144 qemu_chr_fe_write_all(debugout->be, &ch, 1); in io_cpu_write()
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ring_submission.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
31 * set-context and then emitting the batch.
41 if (engine->class == RENDER_CLASS) { in set_hwstam()
42 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
56 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
59 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
67 return sg_page(obj->mm.pages->sgl); in status_page()
81 * The ring status page addresses are no longer next to the rest of in set_hwsp()
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| H A D | intel_workarounds.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014-2018 Intel Corporation
27 * - Context workarounds: workarounds that touch registers that are
37 * - Engine workarounds: the list of these WAs is applied whenever the specific
57 * - GT workarounds: the list of these WAs is applied whenever these registers
63 * - Register whitelist: some workarounds need to be implemented in userspace,
67 * these to/be-whitelisted registers to some special HW registers).
72 * - Workaround batchbuffers: buffers that get executed automatically by the
88 * - Other: There are WAs that, due to their nature, cannot be applied from a
100 wal->gt = gt; in wa_init_start()
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| H A D | intel_ggtt.c | 1 // SPDX-License-Identifier: MIT
13 #include <drm/intel-gtt.h>
46 if (node->color != color) in i915_ggtt_color_adjust()
47 *end -= I915_GTT_PAGE_SIZE; in i915_ggtt_color_adjust()
52 struct drm_i915_private *i915 = ggtt->vm.i915; in ggtt_init_hw()
54 i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT); in ggtt_init_hw()
56 ggtt->vm.is_ggtt = true; in ggtt_init_hw()
58 /* Only VLV supports read-only GGTT mappings */ in ggtt_init_hw()
59 ggtt->vm.has_read_only = IS_VALLEYVIEW(i915); in ggtt_init_hw()
62 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust; in ggtt_init_hw()
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| /openbmc/linux/include/uapi/drm/ |
| H A D | vc4_drm.h | 2 * Copyright © 2014-2015 Broadcom
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
79 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
85 * our commands in BOs, we'd need to do uncached readback from them to do the
116 * order referenced by the record (FS, VS, then CS). Each set of
168 * raster order, with the right-to-left vs left-to-right and
169 * top-to-bottom vs bottom-to-top dictated by
183 /* ID of the perfmon to attach to this job. 0 means no perfmon. */
201 * struct drm_vc4_wait_seqno - ioctl argument for waiting for
213 * struct drm_vc4_wait_bo - ioctl argument for waiting for
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/spi-s3c64xx.h>
25 /* Registers and bit-fields */
108 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
110 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
111 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \
112 __ffs((sdd)->tx_fifomask))
113 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \
114 __ffs((sdd)->rx_fifomask))
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| H A D | spi-cadence-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
65 u8 cs; member
304 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/mx6-ddr.h>
22 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
23 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
34 * Issue the Precharge-All command to the DDR device for both in precharge_all()
40 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
41 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
45 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
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| /openbmc/linux/include/linux/mtd/ |
| H A D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
225 * struct nand_parameters - NAND generic parameters from the parameter page
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| /openbmc/qemu/target/arm/ |
| H A D | helper.c | 6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
24 #include "sysemu/cpu-timers.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
41 assert(ri->fieldoffset); in raw_read()
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| /openbmc/linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos5433-tm2-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h>
48 stdout-path = &serial_1;
56 gpio-keys {
57 compatible = "gpio-keys";
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | s626.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
129 #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
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| /openbmc/linux/drivers/scsi/ |
| H A D | ncr53c8xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** Device driver for the PCI-SCSI NCR538XX controller family.
8 **-----------------------------------------------------------------------------
22 ** Stefan Esser <se@mi.Uni-Koeln.de>
27 **-----------------------------------------------------------------------------
38 ** Support for Fast-20 scsi.
42 ** Support for Fast-40 scsi.
43 ** Support for on-Board RAM.
46 ** Full support for scsi scripts instructions pre-fetching.
51 ** August 18 1997 by Cort <cort@cs.nmt.edu>:
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