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/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
47 int "PMECC Sector Size"
51 Sector size, in bytes, can be 512 or 1024.
64 bool "Support TI Davinci NAND controller"
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H A Domap_gpmc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
15 #include <nand.h>
54 * omap_nand_hwcontrol - Set the address pointers corretly for the
62 int cs = info->cs; in omap_nand_hwcontrol()
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
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H A Datmel_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
18 #include <nand.h>
71 * Return number of ecc bytes per sector according to sector size and
77 * 2-bits 4-bytes 4-bytes
78 * 4-bits 7-bytes 7-bytes
79 * 8-bits 13-bytes 14-bytes
80 * 12-bits 20-bytes 21-bytes
81 * 24-bits 39-bytes 42-bytes
82 * 32-bits 52-bytes 56-bytes
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H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
9 #include <nand.h>
11 #include <linux/dma-direction.h>
19 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, in dma_map_single() argument
24 size = ALIGN(size, ARCH_DMA_MINALIGN); in dma_map_single()
27 invalidate_dcache_range(addr, addr + size); in dma_map_single()
29 flush_dcache_range(addr, addr + size); in dma_map_single()
34 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, in dma_unmap_single() argument
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dsm_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
9 /* Full oob structure as written on the flash */
21 /* one sector is always 512 bytes, but it can consist of two nand pages */
24 /* oob area is also 16 bytes, but might be from two pages */
27 /* This is maximum zone size, and all devices that have more that one zone
28 have this size */
31 /* support for small page nand */
39 static inline int sm_sector_valid(struct sm_oob *oob) in sm_sector_valid() argument
41 return hweight16(oob->data_status) >= 5; in sm_sector_valid()
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H A Domap2.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
145 struct nand_chip nand; member
172 /* NAND ready gpio */
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H A Dnandsim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NAND flash simulator.
9 * Note: NS means "NAND Simulator".
132 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command");
133 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufact…
134 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID…
135 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete…
136 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolet…
139 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
142 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
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H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
29 * on NAND flash memory. Driver uses CDMA mode for
113 /* Size of last data sector. */
115 /* Size of not-last data sector. */
140 /* Transferred data block size for the slave DMA module. */
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/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm97xxx-nand-cs1-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <4>;
9 nand-ecc-step-size = <512>;
10 brcm,nand-oob-sector-size = <16>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;
H A Dbcm97xxx-nand-cs1-bch24.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <24>;
9 nand-ecc-step-size = <1024>;
10 brcm,nand-oob-sector-size = <27>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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/openbmc/linux/drivers/mtd/
H A Dsm_ftl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
16 #include <linux/mtd/nand-ecc-sw-hamming.h>
17 #include "nand/raw/sm_common.h"
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
34 /* ------------------- sysfs attributes ---------------------------------- */
47 strncpy(buf, sm_attr->data, sm_attr->len); in sm_attr_show()
48 return sm_attr->len; in sm_attr_show()
61 vendor = kstrndup(ftl->cis_buffer + SM_CIS_VENDOR_OFFSET, in sm_create_sysfs_attributes()
62 SM_SMALL_PAGE - SM_CIS_VENDOR_OFFSET, GFP_KERNEL); in sm_create_sysfs_attributes()
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/openbmc/u-boot/doc/imx/common/
H A Dmxs.txt1 Booting U-Boot on a MXS processor
4 This document describes the MXS U-Boot port. This document mostly covers topics
8 -----------
14 into the unix command prompt in U-Boot source code root directory.
16 The (=>) introduces a snipped of code that should by typed into U-Boot command
20 --------
23 2) Compiling U-Boot for a MXS based board
24 3) Installation of U-Boot for a MXS based board to SD card
25 4) Installation of U-Boot into NAND flash on a MX28 based board
26 5) Installation of U-Boot into SPI NOR flash on a MX28 based board
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/openbmc/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
94 /* 512B flash cache in the NAND controller HW */
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
249 int sas; /* spare area size, per flash cache */
251 u8 *oob; member
259 u8 *oob, u32 len, u8 dma_cmd);
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
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/openbmc/u-boot/tools/
H A Dmxsboot.c1 // SPDX-License-Identifier: GPL-2.0+
17 #define __round_mask(x, y) ((__typeof__(x))((y)-1))
29 * Layout for 256Mb big NAND with 2048b page size, 64b OOB size and
30 * 128kb erase size.
32 * TWEAK this if you have different kind of NAND chip.
39 * Sector on which the SigmaTel boot partition (0x53) starts.
44 * Each of the U-Boot bootstreams is at maximum 1MB big.
50 /* i.MX28 NAND controller-specific constants. DO NOT TWEAK! */
111 uint32_t nand; member
153 * (page oob size - meta data size) * (bits per byte) in mx28_nand_get_ecc_strength()
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958300k.dts33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
47 stdout-path = "serial0:115200n8";
64 nand@1 {
67 nand-on-flash-bbt;
69 #address-cells = <1>;
70 #size-cells = <1>;
72 nand-ecc-strength = <24>;
73 nand-ecc-step-size = <1024>;
75 brcm,nand-oob-sector-size = <27>;
H A Dbcm958305k.dts33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
47 stdout-path = "serial0:115200n8";
72 nand@1 {
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
H A Dbcm911360_entphn.dts33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
36 #include "dt-bindings/input/input.h"
47 stdout-path = "serial0:115200n8";
50 gpio-keys {
51 compatible = "gpio-keys";
53 button-hook {
74 assigned-clocks =
77 assigned-clock-rates = <525000000>, <300000000>;
86 nand@1 {
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H A Dbcm958625-meraki-mx6x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm-nsp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 pwm-leds {
15 compatible = "pwm-leds";
17 led-1 {
21 max-brightness = <255>;
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H A Dbcm958522er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
78 nand@0 {
81 nand-on-flash-bbt;
83 #address-cells = <1>;
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H A Dbcm958525er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
78 nand@0 {
81 nand-on-flash-bbt;
83 #address-cells = <1>;
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dbcm958742-base.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include "stingray-board-base.dtsi"
37 compatible = "regulator-gpio";
38 regulator-name = "sdio0_vddo_ctrl_reg";
39 regulator-type = "voltage";
40 regulator-min-microvolt = <1800000>;
41 regulator-max-microvolt = <3300000>;
48 compatible = "regulator-gpio";
49 regulator-name = "sdio1_vddo_ctrl_reg";
50 regulator-type = "voltage";
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/openbmc/u-boot/cmd/
H A Dnand.c2 * Driver for NAND support, Rick Bronson
7 * Ported 'dynenv' to 'nand env.oob' command
9 * 'dynenv' -- Dynamic environment offset in NAND OOB
10 * (C) Copyright 2006-2007 OpenMoko, Inc.
11 * Added 16-bit nand support
16 * are not considered a derived work of GPL v2-only code may be distributed
30 #include <nand.h>
50 off = last + mtd->writesize; in nand_dump()
54 datbuf = memalign(ARCH_DMA_MINALIGN, mtd->writesize); in nand_dump()
60 oobbuf = memalign(ARCH_DMA_MINALIGN, mtd->oobsize); in nand_dump()
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/openbmc/u-boot/env/
H A DKconfig20 while U-Boot is running, but once U-Boot exits it will not be
21 stored. U-Boot will therefore always start up with a default
31 - CONFIG_ENV_OFFSET:
32 - CONFIG_ENV_SIZE:
34 These two #defines specify the offset and size of the
41 - CONFIG_ENV_EEPROM_IS_ON_I2C
45 - CONFIG_I2C_ENV_EEPROM_BUS
87 a) The environment occupies one whole flash sector, which is
88 "embedded" in the text segment with the U-Boot code. This
89 happens usually with "bottom boot sector" or "top boot
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/openbmc/linux/drivers/mtd/nand/
H A Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
15 * - external: The ECC engine is outside the NAND pipeline, typically this
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
24 * Some NAND chips can correct themselves the data.
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