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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
H A Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
[all …]
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-ap806.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 /dts-v1/;
53 compatible = "marvell,armada-ap806";
54 #address-cells = <2>;
55 #size-cells = <2>;
63 compatible = "arm,psci-0.2";
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
32 * [25:16] lowest SPI assigned to MSI
34 * [9:0] Numer of SPIs assigned to MSI
50 /* APM X-Gene with GICv2m MSI_IIDR register value */
67 void __iomem *base; /* GICv2m virt address */ member
68 u32 spi_start; /* The SPI number that MSIs start */
[all …]
H A Dirq-mvebu-icu.c5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include <linux/msi.h>
23 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
53 void __iomem *base; member
75 const struct mvebu_icu_subset_data *subset = msi_data->subset_data; in mvebu_icu_init()
77 if (atomic_cmpxchg(&msi_data->initialized, false, true)) in mvebu_icu_init()
80 /* Set 'SET' ICU SPI message address in AP */ in mvebu_icu_init()
81 writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); in mvebu_icu_init()
82 writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); in mvebu_icu_init()
84 if (subset->icu_group != ICU_GRP_NSR) in mvebu_icu_init()
[all …]
H A Dirq-mvebu-odmi.c4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "GIC-ODMI: " fmt
17 #include <linux/msi.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
35 #define NODMIS_MASK (NODMIS_PER_FRAME - 1)
39 void __iomem *base; member
56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
60 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
62 addr = odmi->res.start + GICP_ODMIN_SET; in odmi_compose_msi_msg()
[all …]
H A Dirq-mvebu-sei.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
11 #include <linux/msi.h>
41 void __iomem *base; member
48 /* Lock on MSI allocations/releases */
59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
72 raw_spin_lock_irqsave(&sei->mask_lock, flags); in mvebu_sei_mask_irq()
[all …]
H A Dirq-alpine-msi.c6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/msi.h>
26 #include <asm/msi.h>
63 spin_lock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
65 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, in alpine_msix_allocate_sgi()
67 if (first >= priv->num_spis) { in alpine_msix_allocate_sgi()
68 spin_unlock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
69 return -ENOSPC; in alpine_msix_allocate_sgi()
72 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv2m.c2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system
23 * Server Base System Architecture (SBSA) specification Version 2.2
24 * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
25 * identification registers and with a single non-secure MSI register frame.
32 #include "hw/pci/msi.h"
33 #include "hw/qdev-properties.h"
39 #define TYPE_ARM_GICV2M "arm-gicv2m"
56 qemu_irq spi[GICV2M_NUM_SPI_MAX]; member
66 qemu_irq_pulse(s->spi[irq]); in gicv2m_set_irq()
82 val = (s->base_spi + 32) << 16; in gicv2m_read()
[all …]
/openbmc/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dsdram.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (C) 2007-2010 coresystems GmbH
18 #include <spi.h>
65 return -ENODEV; in read_seed_from_cmos()
70 * SPI flash since they change on every boot and that would wear down in read_seed_from_cmos()
72 * data in SPI flash. in read_seed_from_cmos()
74 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); in read_seed_from_cmos()
77 &pei_data->scrambler_seed_s3); in read_seed_from_cmos()
80 debug("Failed to read from RTC %s\n", dev->name); in read_seed_from_cmos()
85 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); in read_seed_from_cmos()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/openbmc/linux/drivers/media/pci/ddbridge/
H A Dddbridge.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2010-2017 Digital Devices GmbH
31 #include <linux/spi/spi.h>
50 #define DDBRIDGE_VERSION "0.9.33-integrated"
62 u32 base; member
315 int msi; member
354 /* ddbridge-core.c */
/openbmc/linux/drivers/pci/controller/
H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
24 #include <linux/msi.h>
30 #include "../pci-bridge-emul.h"
44 /* PIO registers base address and register offsets */
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
165 /* LMI registers base address and register offsets */
270 void __iomem *base; member
295 writel(val, pcie->base + reg); in advk_writel()
300 return readl(pcie->base + reg); in advk_readl()
[all …]
/openbmc/linux/drivers/acpi/arm64/
H A Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
69 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
76 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
78 * @node: IORT table node to be looked-up
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
/openbmc/linux/drivers/mfd/
H A Dtimberdale.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/platform_data/i2c-ocores.h>
21 #include <linux/platform_data/i2c-xiic.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/xilinx_spi.h>
25 #include <linux/spi/max7301.h>
26 #include <linux/spi/mc33880.h>
50 /*--------------------------------------------------------------------------*/
106 .base = 200
110 .base = 100
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]

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