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/openbmc/linux/drivers/infiniband/hw/mlx4/
H A Dmr.c68 ~0ull, convert_access(acc), 0, 0, &mr->mmr); in mlx4_ib_get_dma_mr()
72 err = mlx4_mr_enable(to_mdev(pd->device)->dev, &mr->mmr); in mlx4_ib_get_dma_mr()
76 mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; in mlx4_ib_get_dma_mr()
82 (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr); in mlx4_ib_get_dma_mr()
429 convert_access(access_flags), n, shift, &mr->mmr); in mlx4_ib_reg_user_mr()
433 err = mlx4_ib_umem_write_mtt(dev, &mr->mmr.mtt, mr->umem); in mlx4_ib_reg_user_mr()
437 err = mlx4_mr_enable(dev->dev, &mr->mmr); in mlx4_ib_reg_user_mr()
441 mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; in mlx4_ib_reg_user_mr()
447 (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr); in mlx4_ib_reg_user_mr()
464 struct mlx4_ib_mr *mmr = to_mmr(mr); in mlx4_ib_rereg_user_mr() local
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/openbmc/linux/drivers/misc/sgi-gru/
H A Dgrufile.c313 unsigned long mmr = 0; in gru_chiplet_cpu_to_mmr() local
327 mmr = UVH_GR0_TLB_INT0_CONFIG + in gru_chiplet_cpu_to_mmr()
330 mmr = UVH_GR1_TLB_INT0_CONFIG + in gru_chiplet_cpu_to_mmr()
337 return mmr; in gru_chiplet_cpu_to_mmr()
359 unsigned long mmr; in gru_chiplet_setup_tlb_irq() local
363 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_setup_tlb_irq()
364 if (mmr == 0) in gru_chiplet_setup_tlb_irq()
390 unsigned long mmr; in gru_chiplet_teardown_tlb_irq() local
396 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_teardown_tlb_irq()
397 if (mmr == 0) in gru_chiplet_teardown_tlb_irq()
[all …]
H A Dgrukservices.h124 * value memory address where MMR value is returned
/openbmc/linux/arch/x86/kernel/apic/
H A Dx2apic_uv_x.c66 panic("UV: error: undefined MMR: %s\n", str); in uv_undefined()
68 pr_crit("UV: error: undefined MMR: %s\n", str); in uv_undefined()
77 unsigned long val, *mmr; in uv_early_read_mmr() local
79 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); in uv_early_read_mmr()
80 val = *mmr; in uv_early_read_mmr()
81 early_iounmap(mmr, sizeof(*mmr)); in uv_early_read_mmr()
146 * The NODE_ID MMR is always at offset 0. in early_set_hub_type()
199 u64 mmr; in uv_tsc_check_sync() local
211 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); in uv_tsc_check_sync()
214 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; in uv_tsc_check_sync()
[all …]
/openbmc/linux/arch/x86/platform/uv/
H A Duv_irq.c21 /* MMR offset and pnode of hub sourcing interrupts for a given irq */
122 * Re-target the irq to the specified CPU and enable the specified MMR located
133 * Disable the specified MMR located on the specified blade so that MSIs are
181 * MMR that defines the MSI that is to be sent to the specified CPU when an
206 * Tear down a mapping of an irq and vector, and disable the specified MMR that
H A Duv_nmi.c42 * We also have to lessen UV Hub MMR accesses as much as possible as this
51 * IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
287 /* Read NMI MMR and check if NMI flag was set by BMC. */
539 /* MMR/PCH NMI flag is clear */ in uv_check_nmi()
555 * Check if this BMC missed setting the MMR NMI flag (or) in uv_check_nmi()
576 /* Need to reset the NMI MMR register, but only once per hub. */
980 /* Clear MMR NMI flag on each hub */ in uv_handle_nmi()
/openbmc/linux/arch/mips/ath25/
H A Dar2315_regs.h45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
48 #define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
50 #define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
51 #define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
52 #define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
54 #define AR2315_UART0_BASE 0x11100000 /* UART MMR */
55 #define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
/openbmc/linux/drivers/infiniband/hw/vmw_pvrdma/
H A Dpvrdma_mr.c93 mr->mmr.mr_handle = resp->mr_handle; in pvrdma_get_dma_mr()
150 mr->mmr.iova = virt_addr; in pvrdma_reg_user_mr()
151 mr->mmr.size = length; in pvrdma_reg_user_mr()
181 mr->mmr.mr_handle = resp->mr_handle; in pvrdma_reg_user_mr()
253 mr->mmr.mr_handle = resp->mr_handle; in pvrdma_alloc_mr()
287 cmd->mr_handle = mr->mmr.mr_handle; in pvrdma_dereg_mr()
/openbmc/linux/arch/x86/include/asm/uv/
H A Duv_hub.h271 * Local & Global MMR space macros.
361 * The window is located at top of ACPI MMR space
459 /* Top two bits indicate the requested address is in MMR space. */
561 * faster MMR access but not all MMRs are accessible in this space.
580 * Access Global MMR space using the MMR space located at the top of physical
729 /* BIOS/Kernel flags exchange MMR */
742 /* BMC sets a bit this MMR non-zero before sending an NMI */
752 atomic_t read_mmr_count; /* count of MMR reads */
754 unsigned long nmi_value; /* last value read from NMI MMR */
H A Dbios.h62 u8 mmr_shift; /* Convert PNode to MMR space offset */
85 u16 pnode; /* Index to MMR and GRU spaces */
/openbmc/linux/arch/ia64/include/asm/uv/
H A Duv_hub.h115 * Local & Global MMR space macros.
180 * faster MMR access but not all MMRs are accessible in this space.
202 * Access Global MMR space using the MMR space located at the top of physical
/openbmc/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dmr.c293 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, in mlx4_mr_hw_get_mpt() argument
297 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); in mlx4_mr_hw_get_mpt()
300 if (mmr->enabled != MLX4_MPT_EN_HW) in mlx4_mr_hw_get_mpt()
310 mmr->enabled = MLX4_MPT_EN_SW; in mlx4_mr_hw_get_mpt()
344 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, in mlx4_mr_hw_write_mpt() argument
360 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); in mlx4_mr_hw_write_mpt()
371 mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK; in mlx4_mr_hw_write_mpt()
372 mmr->enabled = MLX4_MPT_EN_HW; in mlx4_mr_hw_write_mpt()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S155 /* PLL2 DIV2 MMR */
178 /* PLL2 DIV1 MMR */
584 /* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
614 .word 0x01c42030 /* DDR VPTR MMR */
H A Ddm365_lowlevel.c38 * through MMR in dm365_pll1_init()
120 * through MMR in dm365_pll2_init()
/openbmc/u-boot/drivers/i2c/
H A Dat91_i2c.h32 u32 mmr; member
/openbmc/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb.h46 unsigned long mmr; /* memory mode for SDRAM */ member
H A Dmb862xxfbdrv.c624 unsigned long ccf, mmr; in mb862xx_gdc_init() local
650 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2; in mb862xx_gdc_init()
659 outreg(host, GC_MMR, mmr); in mb862xx_gdc_init()
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c138 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
140 * Initialize the SDRAM MMR.
H A Dsdram_arria10.c243 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
679 /* initialize the MMR register */ in ddr_calibration_sequence()
H A Dsdram_gen5.c424 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
427 * Initialize the SDRAM MMR.
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65.dtsi59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
/openbmc/linux/arch/ia64/uv/kernel/
H A Dsetup.c100 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); in uv_setup()
/openbmc/linux/drivers/infiniband/hw/mthca/
H A Dmthca_provider.c923 struct mthca_mr *mmr = to_mmr(mr); in mthca_dereg_mr() local
925 mthca_free_mr(to_mdev(mr->device), mmr); in mthca_dereg_mr()
926 ib_umem_release(mmr->umem); in mthca_dereg_mr()
927 kfree(mmr); in mthca_dereg_mr()
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_s10.h81 /* HMC MMR IO48 registers */

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