Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Arria10 DRAM fixes and Gen5 cache fixes

ddr: socfpga: Clean up ddr_setup()

Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register

ddr: socfpga: Clean up ddr_setup()

Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

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ddr: socfpga: Clean up EMIF reset

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF

ddr: socfpga: Clean up EMIF reset

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

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ddr: socfpga: Fix EMIF clear timeout

The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simp

ddr: socfpga: Fix EMIF clear timeout

The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.

This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

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ddr: socfpga: Fix newline in debug print on A10

The debug print is missing a newline, add it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguye

ddr: socfpga: Fix newline in debug print on A10

The debug print is missing a newline, add it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

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ddr: socfpga: Fix IO in Arria10 DDR driver

The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.

Signed-off-by: M

ddr: socfpga: Fix IO in Arria10 DDR driver

The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c

Signed-off-by: Tom Rini <trini@konsulko.com>

ddr: altera: Add ECC DRAM scrubbing support for Arria10

The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such

ddr: altera: Add ECC DRAM scrubbing support for Arria10

The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the

ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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SPDX: Fixup SPDX tags in a few new files

Signed-off-by: Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

ARM: socfpga: Add DDR driver for Arria 10

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>