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Searched +full:mmc +full:- +full:hs400 +full:- +full:enhanced +full:- +full:strobe (Results 1 – 25 of 50) sorted by relevance

12

/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-edgeble-neu6a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
13 vcc12v_dcin: vcc12v-dcin-regulator {
14 compatible = "regulator-fixed";
15 regulator-name = "vcc12v_dcin";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <12000000>;
19 regulator-max-microvolt = <12000000>;
24 bus-width = <8>;
[all …]
H A Drk3588s-khadas-edge2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
19 stdout-path = "serial2:1500000n8";
24 bus-width = <8>;
25 no-sdio;
26 no-sd;
27 non-removable;
28 mmc-hs400-1_8v;
[all …]
H A Drk3399-nanopc-t4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
11 /dts-v1/;
12 #include "rk3399-nanopi4.dtsi"
15 model = "FriendlyElec NanoPC-T4";
16 compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
18 vcc12v0_sys: vcc12v0-sys {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-boot-on;
[all …]
H A Drk3588-edgeble-neu6b.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
13 vcc12v_dcin: vcc12v-dcin-regulator {
14 compatible = "regulator-fixed";
15 regulator-name = "vcc12v_dcin";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <12000000>;
19 regulator-max-microvolt = <12000000>;
22 vcc5v0_sys: vcc5v0-sys-regulator {
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; in xenon_alloc_emmc_phy()
217 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; in xenon_alloc_emmc_phy()
[all …]
H A Dsdhci-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
9 #include <linux/mmc/host.h>
15 #include "sdhci-cqhci.h"
16 #include "sdhci-pltfm.h"
41 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
62 /* Reset will clear this, so re-enable it */ in brcmstb_reset()
63 if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) in brcmstb_reset()
67 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) in sdhci_brcmstb_hs400es() argument
69 struct sdhci_host *host = mmc_priv(mmc); in sdhci_brcmstb_hs400es()
[all …]
H A Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
22 #include "sdhci-pltfm.h"
76 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
111 offset = addr & (SZ_128M - 1); in dwcmshc_adma_write_desc()
112 tmplen = SZ_128M - offset; in dwcmshc_adma_write_desc()
116 len -= tmplen; in dwcmshc_adma_write_desc()
124 if (pltfm_host->clk) in dwcmshc_get_max_clock()
127 return pltfm_host->clock; in dwcmshc_get_max_clock()
134 return clk_round_rate(pltfm_host->clk, ULONG_MAX); in rk35xx_get_max_clock()
[all …]
H A Dsdhci-sprd.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
12 #include <linux/mmc/host.h>
13 #include <linux/mmc/mmc.h>
23 #include "sdhci-pltfm.h"
106 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
107 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
108 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
109 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
110 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
4 for MMC, SD and SDIO types of cards.
6 This file documents differences between the core properties in mmc.txt
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
[all …]
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Common Properties
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 These properties are common to multiple MMC host controllers. Any host
17 It is possible to assign a fixed index mmcN to an MMC host controller
23 pattern: "^mmc(@.*)?$"
25 "#address-cells":
[all …]
H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
[all …]
H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
17 provides an interface for MMC, SD, and SDIO types of memory cards.
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885-jackpotlte.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 chassis-type = "handset";
28 stdout-path = &serial_2;
38 gpio-keys {
39 compatible = "gpio-keys";
[all …]
H A Dexynos850-e850-96.dts1 // SPDX-License-Identifier: GPL-2.0
3 * WinLink E850-96 board device tree source
8 * Device tree source file for WinLink's E850-96 board which is based on
12 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
20 model = "WinLink E850-96 board";
21 compatible = "winlink,e850-96", "samsung,exynos850";
29 stdout-path = &serial_0;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp418.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15 compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&spi_0_pins>;
28 pinctrl-names = "default";
32 compatible = "micron,n25q128a11", "jedec,spi-nor";
[all …]
H A Dipq9574-rdp433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
15 compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
[all …]
H A Dqdu1000-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
15 chassis-type = "embedded";
22 stdout-path = "serial0:115200n8";
26 xo_board: xo-board-clk {
27 compatible = "fixed-clock";
28 clock-frequency = <19200000>;
29 #clock-cells = <0>;
[all …]
H A Dsda660-inforce-ifc6560.dts1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
18 chassis-type = "embedded"; /* SBC */
26 stdout-path = "serial0:115200n8";
29 gpio-keys {
30 compatible = "gpio-keys";
32 key-volup {
36 debounce-interval = <15>;
41 * Until we hook up type-c detection, we
44 extcon_usb: extcon-usb {
[all …]
H A Dsdm660-xiaomi-lavender.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/input/gpio-keys.h>
18 chassis-type = "handset";
25 #address-cells = <2>;
26 #size-cells = <2>;
29 stdout-path = "serial0:115200n8";
32 compatible = "simple-framebuffer";
41 vph_pwr: vph-pwr-regulator {
[all …]
/openbmc/linux/include/linux/mmc/
H A Dhost.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/mmc/host.h
12 #include <linux/fault-inject.h>
14 #include <linux/mmc/core.h>
15 #include <linux/mmc/card.h>
16 #include <linux/mmc/pm.h>
17 #include <linux/dma-direction.h>
18 #include <linux/blk-crypto-profile.h>
141 * ios->clock might be 0. For some controllers, setting 0Hz
151 * 1 for a read-only card
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/sprd,sc9860-clk.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
67 ap-apb {
68 compatible = "simple-bus";
[all …]
/openbmc/linux/drivers/mmc/core/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/fault-inject.h>
16 #include <linux/mmc/card.h>
17 #include <linux/mmc/host.h>
55 struct mmc_host *host = s->private; in mmc_ios_show()
56 struct mmc_ios *ios = &host->ios; in mmc_ios_show()
59 seq_printf(s, "clock:\t\t%u Hz\n", ios->clock); in mmc_ios_show()
60 if (host->actual_clock) in mmc_ios_show()
61 seq_printf(s, "actual clock:\t%u Hz\n", host->actual_clock); in mmc_ios_show()
62 seq_printf(s, "vdd:\t\t%u ", ios->vdd); in mmc_ios_show()
[all …]
H A Dhost.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/core/host.c
6 * Copyright (C) 2007-2008 Pierre Ossman
9 * MMC host class device management
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/card.h>
25 #include <linux/mmc/slot-gpio.h>
30 #include "slot-gpio.h"
47 if (!host->bus_ops) in mmc_host_class_prepare()
51 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare()
[all …]
H A Dbus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/core/bus.c
8 * MMC card bus driver model
20 #include <linux/mmc/card.h>
21 #include <linux/mmc/host.h>
36 switch (card->type) { in type_show()
38 return sysfs_emit(buf, "MMC\n"); in type_show()
46 return -EFAULT; in type_show()
65 switch (card->type) { in mmc_bus_uevent()
67 type = "MMC"; in mmc_bus_uevent()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-evb.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
14 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
15 "google,rk3399evb-rev2";
18 stdout-path = &uart2;
19 u-boot,spl-boot-order = \
23 vdd_center: vdd-center {
[all …]

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