Home
last modified time | relevance | path

Searched +full:mac +full:- +full:clk +full:- +full:rx (Results 1 – 25 of 248) sorted by relevance

12345678910

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: snps,dwmac.yaml#
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 nvmem-cells:
40 nvmem-cell-names:
[all …]
/openbmc/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
58 /* Rx ring */
79 /* Scratch page to use when rx skb alloc fails */
90 struct clk *clk; member
93 struct clk *rclk;
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
[all …]
/openbmc/u-boot/drivers/net/
H A Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0+
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2016-2018 Socionext inc.
7 #include <clk.h>
34 /* MAC Register Group */
36 #define AVE_RXCR 0x204 /* RX Setup */
37 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
38 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
48 #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
54 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
[all …]
H A Dravb.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
12 #include <clk.h>
124 struct clk clk; member
135 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1); in ravb_invalidate_dcache()
143 struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx]; in ravb_send()
149 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len); in ravb_send()
150 desc->dptr = (uintptr_t)packet; in ravb_send()
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) in ravb_send()
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); in ravb_send()
[all …]
H A Dsh_eth.c1 // SPDX-License-Identifier: GPL-2.0+
3 * sh_eth.c - Driver for Renesas ethernet controller.
22 #include <clk.h>
53 start &= ~(line_size - 1); \
54 end = ((end + line_size - 1) & ~(line_size - 1)); \
67 struct sh_eth_info *port_info = &eth->port_info[eth->port]; in sh_eth_send_common()
71 ret = -EINVAL; in sh_eth_send_common()
79 ret = -EFAULT; in sh_eth_send_common()
85 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); in sh_eth_send_common()
86 port_info->tx_desc_cur->td1 = len << 16; in sh_eth_send_common()
[all …]
/openbmc/linux/drivers/net/ethernet/
H A Dethoc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
8 * Written by Thierry Reding <thierry.reding@avionic-design.de>
11 #include <linux/dma-mapping.h>
13 #include <linux/clk.h>
64 #define MODER_NBO (1 << 8) /* no back-off */
152 /* RX buffer descriptor */
154 #define RX_BD_CRC (1 << 1) /* RX CRC error */
177 * struct ethoc - driver-private device structure
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
[all …]
/openbmc/linux/drivers/net/ethernet/socionext/
H A Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
40 #define AVE_RXCR 0x204 /* RX Setup */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
52 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */
70 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
[all …]
/openbmc/linux/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <linux/clk.h>
34 #include "sun4i-emac.h"
36 #define DRV_NAME "sun4i-emac"
41 static int debug = -1; /* defaults above */;
73 struct clk *clk; member
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
110 if (db->speed == SPEED_100) in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
[all …]
/openbmc/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_driver.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/nvmem-consumer.h>
13 #include <linux/clk.h>
27 struct spl2sw_mac *mac = netdev_priv(ndev); in spl2sw_ethernet_open() local
28 struct spl2sw_common *comm = mac->comm; in spl2sw_ethernet_open()
31 netdev_dbg(ndev, "Open port = %x\n", mac->lan_port); in spl2sw_ethernet_open()
33 comm->enable |= mac->lan_port; in spl2sw_ethernet_open()
37 /* Enable TX and RX interrupts */ in spl2sw_ethernet_open()
38 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
40 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
[all …]
H A Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
27 #define MAC_INT_RX_DONE_L BIT(5) /* RX Low Priority Done */
28 #define MAC_INT_RX_DONE_H BIT(4) /* RX High Priority Done */
32 #define MAC_INT_RX_DES_ERR BIT(0) /* Rx Descriptor Error */
63 /* Wt mac ad0 */
77 /* W mac 15_0 bus */
80 /* W mac 47_16 bus */
154 /* MAC force mode */
171 #define RX_QUEUE0_DESC_NUM 16 /* # of descriptors in RX queue 0 */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
9 #include <linux/clk.h>
75 struct ingenic_mac *mac = plat_dat->bsp_priv; in ingenic_mac_init() local
78 if (mac->soc_info->set_mode) { in ingenic_mac_init()
79 ret = mac->soc_info->set_mode(plat_dat); in ingenic_mac_init()
89 struct ingenic_mac *mac = plat_dat->bsp_priv; in jz4775_mac_set_mode() local
92 switch (plat_dat->mac_interface) { in jz4775_mac_set_mode()
96 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); in jz4775_mac_set_mode()
102 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n"); in jz4775_mac_set_mode()
[all …]
/openbmc/linux/drivers/net/ethernet/nxp/
H A Dlpc_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
23 #include <linux/soc/nxp/lpc32xx-misc.h>
25 #define MODNAME "lpc-eth"
35 * Ethernet MAC controller Register offsets
317 if (dev && dev->of_node) { in lpc_phy_interface_mode()
318 const char *mode = of_get_property(dev->of_node, in lpc_phy_interface_mode()
319 "phy-mode", NULL); in lpc_phy_interface_mode()
328 if (dev && dev->of_node) in use_iram_for_net()
329 return of_property_read_bool(dev->of_node, "use-iram"); in use_iram_for_net()
[all …]
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2004-2008 SMSC
5 * Copyright (C) 2005-2008 ARM
22 #include <linux/clk.h>
56 #define SMSC_MDIONAME "smsc911x-mdio"
57 #define SMSC_DRV_VERSION "2008-10-21"
141 struct clk *clk; member
145 #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
149 if (pdata->config.flags & SMSC911X_USE_32BIT) in __smsc911x_reg_read()
150 return readl(pdata->ioaddr + reg); in __smsc911x_reg_read()
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
45 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
46 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
51 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
52 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
53 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 * hardware maximum rx/tx packet size including FCS, max mtu is
30 * actually 2047, but if we set max rx size register to 2047 we won't
199 /* mac irq, rx_dma irq, tx_dma irq */
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
215 /* dma channel id for rx */
218 /* number of dma desc in rx ring */
221 /* cpu view of rx dma ring */
224 /* current number of armed descriptor given to hardware for rx */
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/
H A Dhisi_femac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hisilicon Fast Ethernet MAC Driver
9 #include <linux/clk.h>
18 /* MAC control register list */
38 #define HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
84 #define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - \
86 /* software tx and rx queue number, should be power of 2 */
91 #define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
111 struct clk *clk; member
130 val = readl(priv->glb_base + GLB_IRQ_ENA); in hisi_femac_irq_enable()
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
18 #include "emac-mac.h"
19 #include "emac-phy.h"
20 #include "emac-sgmii.h"
84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
100 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
101 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
109 irq->mask |= rx_q->intr; in emac_napi_rtx()
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Atheros AR71xx built-in ethernet mac driver
11 * David Bauer <mail@david-bauer.net>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
17 * Jo-Philipp Wich <jo@mein.io>
39 #include <linux/clk.h>
43 /* For our NAPI weight bigger does *NOT* mean better - it means more
44 * D-cache misses and lots more wasted cycles than we'll ever
73 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
[all …]

12345678910