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/openbmc/linux/Documentation/driver-api/surface_aggregator/clients/
H A Ddtx.rst39 * **Latch:**
55 Latch States
58 The latch mechanism has two major states: *open* and *closed*. In the
62 The latch can additionally be locked and, correspondingly, unlocked, which
66 documentation for the detachment procedure below. By default, the latch is
82 instructions/commands. In case the latch is unlocked, the led will flash
83 green. If the latch has been locked, the led will be solid red
93 - If the latch is unlocked, the EC will open the latch and the clipboard
98 - If the latch is locked, the EC will *not* open the latch, meaning the
111 latch, after which the user can separate clipboard and base.
[all …]
/openbmc/qemu/hw/misc/
H A Dmos6522.c160 /* the timer goes down from latch to -1 (period of latch + 2) */ in get_counter()
164 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); in get_counter()
165 counter = (ti->latch - counter) & 0xffff; in get_counter()
199 /* the timer goes down from latch to -1 (period of latch + 2) */ in get_next_irq_time()
203 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); in get_next_irq_time()
204 counter = (ti->latch - counter) & 0xffff; in get_next_irq_time()
209 next_time = d + ti->latch + 1; in get_next_irq_time()
211 next_time = d + ti->latch + 2; in get_next_irq_time()
215 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); in get_next_irq_time()
349 val = s->timers[0].latch & 0xff; in mos6522_read()
[all …]
/openbmc/linux/include/linux/mfd/abx500/
H A Dab8500.h74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
7 title: GPIO latch controller
43 of number of latches and the number of inputs per latch is derived from
48 const: gpio-latch
53 description: Array of GPIOs to be used to clock a latch
56 description: Array of GPIOs to be used as inputs per latch
59 description: Delay in nanoseconds to wait after the latch inputs have been
80 gpio-latch {
84 compatible = "gpio-latch";
H A Dsprd,gpio-eic.yaml19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
48 - sprd,sc9860-eic-latch
58 - sprd,ums512-eic-latch
59 - const: sprd,sc9860-eic-latch
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dpmc.json55 "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
70 "BriefDescription": "Cycles when at least one thread has the run latch set."
80 "BriefDescription": "Cycles when the run latch is set for all threads."
90 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
105 "BriefDescription": "Processor cycles gated by the run latch."
130 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
200 "BriefDescription": "PowerPC instruction completed while the run latch is set."
/openbmc/linux/drivers/clk/ti/
H A Dmux.c81 ti_clk_latch(&mux->reg, mux->latch); in ti_clk_mux_set_parent()
125 s8 latch, u8 clk_mux_flags, u32 *table) in _register_mux() argument
146 mux->latch = latch; in _register_mux()
175 s32 latch = -EINVAL; in of_mux_clk_setup() local
194 of_property_read_u32(node, "ti,latch-bit", &latch); in of_mux_clk_setup()
211 flags, &reg, shift, mask, latch, clk_mux_flags, in of_mux_clk_setup()
235 mux->latch = -EINVAL; in ti_clk_build_component_mux()
/openbmc/linux/drivers/gpio/
H A Dgpio-latch.c3 * GPIO latch driver
37 * the number of inputs per latch is derived from the number of GPIOs given
78 int latch = offset / priv->n_latched_gpios; in gpio_latch_set_unlocked() local
85 test_bit(latch * priv->n_latched_gpios + i, priv->shadow)); in gpio_latch_set_unlocked()
88 set(priv->clk_gpios->desc[latch], 1); in gpio_latch_set_unlocked()
90 set(priv->clk_gpios->desc[latch], 0); in gpio_latch_set_unlocked()
202 .compatible = "gpio-latch",
210 .name = "gpio-latch",
219 MODULE_DESCRIPTION("GPIO latch driver");
H A Dgpio-eic-sprd.c67 * debounce EIC, latch EIC, async EIC and sync EIC,
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
106 "eic-debounce", "eic-latch", "eic-async",
481 * The debounce EIC and latch EIC can only support level trigger, so we in sprd_eic_toggle_trigger()
579 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async in sprd_eic_irq_handler()
689 .compatible = "sprd,sc9860-eic-latch",
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Durquell.h60 #define LATCHCR_OFS 0x3000 /* Latch control register */
61 #define LATCUAR_OFS 0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS 0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
/openbmc/qemu/hw/block/
H A Dswim.c25 /* IWM latch bits */
284 uint8_t latch, reg, ism_bit; in iwmctrl_write() local
288 /* A3-A1 select a latch, A0 specifies the value */ in iwmctrl_write()
289 latch = (addr >> 1) & 7; in iwmctrl_write()
291 swimctrl->iwm_latches |= (1 << latch); in iwmctrl_write()
293 swimctrl->iwm_latches &= ~(1 << latch); in iwmctrl_write()
348 uint8_t latch, reg, value; in iwmctrl_read() local
352 /* A3-A1 select a latch, A0 specifies the value */ in iwmctrl_read()
353 latch = (addr >> 1) & 7; in iwmctrl_read()
355 swimctrl->iwm_latches |= (1 << latch); in iwmctrl_read()
[all …]
/openbmc/qemu/hw/xen/
H A Dxen_pt_msi.c29 #define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)] macro
349 entry->addr = entry->latch(LOWER_ADDR) | in xen_pt_msix_update_one()
350 ((uint64_t)entry->latch(UPPER_ADDR) << 32); in xen_pt_msix_update_one()
351 entry->data = entry->latch(DATA); in xen_pt_msix_update_one()
380 xen_pt_msix_update_one(s, i, msix->msix_entry[i].latch(VECTOR_CTRL)); in xen_pt_msix_update()
429 assert(!(offset % sizeof(*e->latch))); in get_entry_value()
430 return e->latch[offset / sizeof(*e->latch)]; in get_entry_value()
435 assert(!(offset % sizeof(*e->latch))); in set_entry_value()
436 e->latch[offset / sizeof(*e->latch)] = val; in set_entry_value()
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_uniphier.c21 * - Divisor latch at 9, no divisor latch access bit
30 /* Divisor Latch Register */
110 /* Divisor latch access bit does not exist. */ in uniphier_serial_out()
144 * This hardware does not have the divisor latch access bit.
145 * The divisor latch register exists at different address.
/openbmc/linux/include/linux/
H A Dseqlock.h638 * Latch sequence counters (seqcount_latch_t)
666 * raw_read_seqcount_latch() - pick even/odd latch data copy
686 * read_seqcount_latch() - pick even/odd latch data copy
731 * raw_write_seqcount_latch() - redirect latch readers to even/odd copy
742 * write_seqcount_latch_begin() - redirect latch readers to odd copy
745 * The latch technique is a multiversion concurrency control method that allows
752 * latch allows the same for non-atomic updates. The trade-off is doubling the
769 * void latch_modify(struct latch_struct *latch, ...)
771 * write_seqcount_latch_begin(&latch->seq);
772 * modify(latch->data[0], ...);
[all …]
H A Dserial_8250.h25 * UART divisor latch read.
29 * Write @value into UART divisor latch.
116 * UART divisor latch read.
120 * Write @value into UART divisor latch.
/openbmc/linux/kernel/time/
H A Dclockevents.c32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
44 * not equal latch, we know that the above shift overflowed. in cev_delta2ns()
46 if ((clc >> evt->shift) != (u64)latch) in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
62 * we would end up with a latch value larger than the upper in cev_delta2ns()
79 * clockevent_delta2ns - Convert a latch value (device ticks) to nanoseconds
80 * @latch: value to convert
83 * Math helper, returns latch value converted to nanoseconds (bound checked)
85 u64 clockevent_delta2ns(unsigned long latch, struct clock_event_device *evt) in clockevent_delta2ns() argument
[all …]
/openbmc/skeleton/libopenbmc_intf/
H A Dgpio_configs.c54 /* Latch out - optional */ in read_power_gpios()
56 const cJSON* latch = cJSON_GetObjectItem(power_config, "latch_out"); in read_power_gpios() local
57 if (latch != NULL) in read_power_gpios()
59 gpios->power_gpio.latch_out.name = g_strdup(latch->valuestring); in read_power_gpios()
60 g_print("Power GPIO latch output: %s\n", in read_power_gpios()
/openbmc/linux/arch/sh/include/asm/
H A Dsmc37c93x.h67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
127 #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
/openbmc/skeleton/op-pwrctl/
H A Dpower_control_obj.c307 /* If there's a latch, it should be enabled following changes to the in on_set_power_state()
308 * power pins' states. This commits the changes to the latch states. */ in on_set_power_state()
316 g_print("PowerControl ERROR failed to open latch %s rc=%d\n", in on_set_power_state()
320 /* Make the latch transparent for as brief of a time as possible. */ in on_set_power_state()
323 g_print("PowerControl ERROR failed to assert latch %s rc=%d\n", in on_set_power_state()
326 g_print("PowerControl asserted latch %s\n", in on_set_power_state()
331 g_print("PowerControl ERROR failed to clear latch %s rc=%d\n", in on_set_power_state()
374 if(power_gpio->latch_out.name != NULL) { /* latch is optional */ in set_up_gpio()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dpipeline.json269 "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
275 "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
276 "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
281 "BriefDescription": "Cycles run latch is set and core is in ST mode",
/openbmc/linux/arch/powerpc/platforms/powermac/
H A Dtime.c53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
195 /* set the latch to `count' */ in via_calibrate_decr()
/openbmc/linux/drivers/clocksource/
H A Dtimer-ixp4xx.c48 u32 latch; member
138 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK; in ixp4xx_set_periodic()
177 * So make sure the latch is the best value with the two least in ixp4xx_timer_register()
180 tmr->latch = DIV_ROUND_CLOSEST(timer_freq, in ixp4xx_timer_register()
H A Di8253.c55 * jiffies was incremented and the point where we latch the in i8253_read()
59 outb_p(0x00, PIT_MODE); /* latch the count ASAP */ in i8253_read()
63 /* VIA686a test code... reset the latch if count > max + 1 */ in i8253_read()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_spl_simple.c34 /* Begin command latch cycle */ in nand_command()
47 /* Latch in address */ in nand_command()
83 /* Begin command latch cycle */ in nand_command()
99 /* Latch in address */ in nand_command()

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