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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
[all …]
/openbmc/linux/drivers/clk/ti/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Tero Kristo (t-kristo@ti.com)
16 s8 latch; member
32 s8 latch; member
87 #define CLK(dev, con, ck) \ argument
93 .clk = ck, \
142 * struct ti_dt_clk - OMAP DT clock alias declarations
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795-sony-xperia-m5.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "sony,xperia-m5", "mediatek,mt6795";
15 chassis-type = "handset";
30 reserved_memory: reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
38 no-map;
42 preloader-region@44800000 {
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/openbmc/u-boot/drivers/mmc/
H A Dmtk-sd.c1 // SPDX-License-Identifier: GPL-2.0
268 /* whether to use gpio detection or built-in hw detection */
290 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); in msdc_reset_hw()
292 readl_poll_timeout(&host->base->msdc_cfg, reg, in msdc_reset_hw()
300 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); in msdc_fifo_clr()
302 readl_poll_timeout(&host->base->msdc_fifocs, reg, in msdc_fifo_clr()
308 return (readl(&host->base->msdc_fifocs) & in msdc_fifo_rx_bytes()
314 return (readl(&host->base->msdc_fifocs) & in msdc_fifo_tx_bytes()
322 switch (cmd->resp_type) { in msdc_cmd_find_resp()
349 u32 opcode = cmd->cmdidx; in msdc_cmd_prepare_raw_cmd()
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/openbmc/linux/drivers/mmc/host/
H A Dmtk-sd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
34 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
89 /*--------------------------------------------------------------------------*/
91 /*--------------------------------------------------------------------------*/
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
136 writel(val, hw->hw_addr + reg); in __ew32()
140 * e1000_regdump - register printout routine
150 switch (reginfo->ofs) { in e1000_regdump()
164 pr_info("%-15s %08x\n", in e1000_regdump()
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