| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | qcom,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
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| H A D | msm,iommu-v0.txt | 1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
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| H A D | arm,smmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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| H A D | renesas,ipmmu-vmsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
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| /openbmc/qemu/docs/system/arm/ |
| H A D | virt.rst | 1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - Flash memory
35 - Either one or two PL011 UARTs for the NonSecure World
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| /openbmc/qemu/docs/devel/ |
| H A D | vfio-iommufd.rst | 9 for assigned devices. While the legacy kernel interface is group-centric,
10 the new iommufd interface is device-centric, relying on device fd and iommufd.
19 secure context and dma management interface. The below diagram shows how it
25 +-------+ +----------+ +-----+ +-----+
27 +---+---+ +----+-----+ +--+--+ +--+--+ +----------------------+
29 | | | | +------------+---------+
30 +---V-----------V-----------V--------V----+ /
31 | VFIOAddressSpace | <------------+
34 +-------+----------------------------+----+
37 +-------V------+ +--------V----------+
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| /openbmc/linux/drivers/iommu/arm/arm-smmu/ |
| H A D | qcom_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
69 struct mutex init_mutex; /* Protects iommu pointer */
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| /openbmc/qemu/hw/misc/ |
| H A D | tz-mpc.c | 21 #include "hw/misc/tz-mpc.h"
22 #include "hw/qdev-properties.h"
24 /* Our IOMMU has two IOMMU indexes, one for secure transactions and one for
25 * non-secure transactions.
76 qemu_set_irq(s->irq, s->int_stat && s->int_en); in tz_mpc_irq_update()
83 * must call the IOMMU notifiers for the changed blocks. in tz_mpc_iommu_notify()
87 .addr_mask = s->blocksize - 1, in tz_mpc_iommu_notify()
90 hwaddr addr = lutidx * s->blocksize * 32; in tz_mpc_iommu_notify()
93 for (i = 0; i < 32; i++, addr += s->blocksize) { in tz_mpc_iommu_notify()
110 memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, event); in tz_mpc_iommu_notify()
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| H A D | trace-events | 3 # allwinner-cpucfg.c
4 allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32
8 # allwinner-h3-dramc.c
18 # allwinner-r40-dramc.c
32 # allwinner-sid.c
36 # allwinner-sramc.c
108 # mps2-scc.c
115 # mps2-fpgaio.c
120 # msf2-sysreg.c
121 msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRI…
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 is expected to be accompanied with an IOMMU based DMA protection.
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
47 knowing about it. There are ways to prevent this by setting up an IOMMU but
64 In BIOS settings this is typically called *Unique ID*.
66 secure
68 addition to UUID the device (if it supports secure connect) is sent
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| /openbmc/qemu/docs/system/s390x/ |
| H A D | protvirt.rst | 12 -------------
26 -----------------------------------
32 -object s390-pv-guest,id=pv0 \
33 -machine confidential-guest-support=pv0
38 * Enable the IOMMU by default for all I/O devices
48 ------------
50 A secure guest image can either be loaded from disk or supplied on the
52 s390-ccw BIOS. I.e., the bootmap is interpreted, multiple components
56 the OS kernel. The secure image has another component prepended
58 transition into secure mode.
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| H A D | vfio-ap.rst | 7 ------------
19 -------------------------
47 example, to set a secure private key for the domain.
51 An AP queue is the means by which an AP command-request message is sent to an
53 comprised of an AP adapter ID (APID) and an AP queue index (APQI). The
57 which the AP command-request message is to be sent for processing.
63 * NQAP: to enqueue an AP command-request message to a queue
64 * DQAP: to dequeue an AP command-reply message from a queue
73 ----------------------------------------------
84 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | vfio.rst | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
9 systems such as Freescale PAMU. The VFIO driver is an IOMMU/device
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
27 which has no notion of IOMMU protection, limited interrupt support,
33 secure, more featureful userspace driver environment than UIO.
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| H A D | vfio-mediated-device.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
17 The number of use cases for virtualizing DMA devices that do not have built-in
25 an IOMMU/device-agnostic framework for exposing direct device access to user
26 space in a secure, IOMMU-protected environment. This framework is used for
37 * Add a mediated device to and remove it from an IOMMU group
44 The following high-level block diagram shows the main components and interfaces
48 +---------------+
50 | +-----------+ | mdev_register_driver() +--------------+
51 | | | +<------------------------+ |
53 | | bus | +------------------------>+ vfio_mdev.ko |<-> VFIO user
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| /openbmc/qemu/hw/arm/ |
| H A D | virt.c | 2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/core/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
63 #include "hw/qdev-properties.h"
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| H A D | virt-acpi-build.c | 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
32 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
49 #include "hw/pci-host/gpex.h"
53 #include "hw/platform-bus.h"
60 #include "hw/virtio/virtio-acpi.h"
72 for (i = 0; i < ms->smp.cpus; i++) { in acpi_dsdt_add_cpus()
88 aml_append(crs, aml_memory32_fixed(uart_memmap->base, in acpi_dsdt_add_uart()
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| /openbmc/linux/drivers/iommu/ |
| H A D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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| /openbmc/linux/Documentation/arch/x86/ |
| H A D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
22 Use of SVA requires IOMMU support in the platform. IOMMU is also
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
53 record, and the PASID (process address space ID) of the current process.
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
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| /openbmc/qemu/linux-headers/linux/ |
| H A D | iommufd.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
23 * - ENOTTY: The IOCTL number itself is not supported at all
24 * - E2BIG: The IOCTL number is supported, but the provided structure has
25 * non-zero in a part the kernel does not understand.
26 * - EOPNOTSUPP: The IOCTL number is supported, and the structure is
29 * - EINVAL: Everything about the IOCTL was understood, but a field is not
31 * - ENOENT: An ID or IOVA provided does not exist.
32 * - ENOMEM: Out of memory.
33 * - EOVERFLOW: Mathematics overflowed.
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| /openbmc/linux/Documentation/arch/s390/ |
| H A D | vfio-ap.rst | 13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
45 sub-directory::
57 domain can be configured with a secure private key used for clear key
65 usage domain; for example, to set the secure private key for the control
76 significant bit, correspond to domains 0-255.
82 comprised of an AP adapter ID (APID) and an AP queue index (APQI). The
111 * NQAP: to enqueue an AP command-request message to a queue
112 * DQAP: to dequeue an AP command-reply message from a queue
132 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
137 corresponds to an AP queue index (APQI) from 0-255. If a bit is set, the
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-thunderbolt | 29 de-authorization of devices. Value of 1 means user can
30 de-authorize PCIe tunnel by writing 0 to authorized
37 Description: This attribute tells whether the system uses IOMMU
38 for DMA protection. Value of 1 means IOMMU is used 0 means
53 secure Require devices that support secure connect at
78 0 The device will be de-authorized (only supported if
87 0 The device will be de-authorized (only supported if
117 Description: When a devices supports Thunderbolt secure connect it will
119 authorization to use the secure connection method instead.
127 Description: This attribute contains id of this device extracted from
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := id.o io.o control.o devices.o fb.o pm.o \
8 common.o dma.o omap-headsmp.o sram.o
10 hwmod-common = omap_hwmod.o \
15 clock-common = clock.o
16 secure-common = omap-smc.o omap-secure.o
18 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
19 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
20 obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
21 obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
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| H A D | pdata-quirks.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/platform_data/pinctrl-single.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22 #include <linux/platform_data/iommu-omap.h>
23 #include <linux/platform_data/ti-sysc.h>
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/ti-prm.h>
30 #include "common-board-devices.h"
33 #include "omap-secure.h"
58 * Note that if the pins are used for MMC1, pbias-regulator
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| /openbmc/linux/drivers/iommu/iommufd/ |
| H A D | device.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES
6 #include <linux/iommu.h>
8 #include "../iommu-priv.h"
25 WARN_ON(igroup->hwpt || !list_empty(&igroup->device_list)); in iommufd_group_release()
27 xa_cmpxchg(&igroup->ictx->groups, iommu_group_id(igroup->group), igroup, in iommufd_group_release()
29 iommu_group_put(igroup->group); in iommufd_group_release()
30 mutex_destroy(&igroup->lock); in iommufd_group_release()
36 kref_put(&group->ref, iommufd_group_release); in iommufd_put_group()
45 * group ID's cannot be re-used until the group is put back which does in iommufd_group_try_get()
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8916.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
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