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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/etcd/etcd/
H A D0001-xxhash-bump-to-v2.1.2.patch44 github.com/beorn7/perks v1.0.1 // indirect
45 - github.com/cespare/xxhash/v2 v2.1.1 // indirect
46 + github.com/cespare/xxhash/v2 v2.1.2 // indirect
47 github.com/coreos/go-semver v0.3.0 // indirect
48 github.com/coreos/go-systemd/v22 v22.3.2 // indirect
49 github.com/gogo/protobuf v1.3.2 // indirect
70 github.com/beorn7/perks v1.0.1 // indirect
71 - github.com/cespare/xxhash/v2 v2.1.1 // indirect
72 + github.com/cespare/xxhash/v2 v2.1.2 // indirect
73 github.com/coreos/go-semver v0.3.0 // indirect
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Dvirtio.c277 QVRingIndirectDesc *indirect = g_malloc(sizeof(*indirect)); in qvring_indirect_desc_setup() local
279 indirect->index = 0; in qvring_indirect_desc_setup()
280 indirect->elem = elem; in qvring_indirect_desc_setup()
281 indirect->desc = guest_alloc(alloc, sizeof(struct vring_desc) * elem); in qvring_indirect_desc_setup()
284 /* indirect->desc[i].addr */ in qvring_indirect_desc_setup()
285 qvirtio_writeq(d, qs, indirect->desc + (16 * i), 0); in qvring_indirect_desc_setup()
294 /* indirect->desc[i].flags */ in qvring_indirect_desc_setup()
295 qvirtio_writew(d, qs, indirect->desc + (16 * i) + 12, in qvring_indirect_desc_setup()
298 /* indirect->desc[i].next */ in qvring_indirect_desc_setup()
299 qvirtio_writew(d, qs, indirect->desc + (16 * i) + 14, i + 1); in qvring_indirect_desc_setup()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Drelocate.S18 * However, these ROM-based vectors actually just perform indirect
23 * 0x00000000 reset indirect branch to [0x00000014]
24 * 0x00000004 undefined instruction indirect branch to [0xfffffef0]
25 * 0x00000008 software interrupt indirect branch to [0xfffffef4]
26 * 0x0000000c prefetch abort indirect branch to [0xfffffef8]
27 * 0x00000010 data abort indirect branch to [0xfffffefc]
29 * 0x00000018 IRQ indirect branch to [0xffffff00]
30 * 0x0000001c FIQ indirect branch to [0xffffff04]
33 * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
43 add r0, r0, r1 /* skip to indirect table */
[all …]
/openbmc/linux/fs/befs/
H A Ddatastream.c187 /* Size of indirect block */ in befs_count_blocks()
189 metablocks += ds->indirect.len; in befs_count_blocks()
192 * Double indir block, plus all the indirect blocks it maps. in befs_count_blocks()
193 * In the double-indirect range, all block runs of data are in befs_count_blocks()
195 * how many data block runs are in the double-indirect region, in befs_count_blocks()
196 * and from that we know how many indirect blocks it takes to in befs_count_blocks()
197 * map them. We assume that the indirect blocks are also in befs_count_blocks()
243 * as in the indirect region code).
291 * blockno is in the indirect region of the datastream.
297 * For each block in the indirect run of the datastream, read
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dbranch.json24 …"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch tha…
27 …"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that…
30 …"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts wh…
33 …"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts whe…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
42 …"PublicDescription": "Indirect branch with predicted address executed. This event counts when any …
45 …"BriefDescription": "Indirect branch with predicted address executed. This event counts when any i…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dbranch.json24 …"PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whi…
27 …"BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whic…
30 …"PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts w…
33 …"BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts wh…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
42 …"PublicDescription": "Indirect branch with predicted address executed.This event counts when any i…
45 …"BriefDescription": "Indirect branch with predicted address executed.This event counts when any in…
/openbmc/linux/fs/minix/
H A Ditree_common.c8 } Indirect; typedef
12 static inline void add_chain(Indirect *p, struct buffer_head *bh, block_t *v) in add_chain()
18 static inline int verify_chain(Indirect *from, Indirect *to) in verify_chain()
30 static inline Indirect *get_branch(struct inode *inode, in get_branch()
33 Indirect chain[DEPTH], in get_branch()
37 Indirect *p = chain; in get_branch()
73 Indirect *branch) in alloc_branch()
116 Indirect chain[DEPTH], in splice_branch()
117 Indirect *where, in splice_branch()
136 /* had we spliced it onto indirect block? */ in splice_branch()
[all …]
/openbmc/linux/fs/ext4/
H A Dindirect.c3 * linux/fs/ext4/indirect.c
35 } Indirect; typedef
37 static inline void add_chain(Indirect *p, struct buffer_head *bh, __le32 *v) in add_chain()
49 * followed (on disk) by an indirect block.
53 * data blocks at leaves and indirect blocks in intermediate nodes.
60 * we need to know is the capacity of indirect blocks (taken from the
66 * indirect block) is spelled differently, because otherwise on an
115 * ext4_get_branch - read the chain of indirect blocks leading to data
118 * @offsets: offsets of pointers in inode/indirect blocks
128 * for i>0) and chain[i].bh points to the buffer_head of i-th indirect
[all …]
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dspectre.rst62 execution of indirect branches to leak privileged memory.
93 execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
95 indirect branches can be influenced by an attacker, causing gadget code
102 In Spectre variant 2 attacks, the attacker can steer speculative indirect
104 buffer of a CPU used for predicting indirect branch addresses. Such
105 poisoning could be done by indirect branching into existing code,
106 with the address offset of the indirect branch under the attacker's
109 this could cause privileged code's indirect branch to jump to a gadget
130 steer its indirect branch speculations to gadget code, and measure the
135 Branch History Buffer (BHB) to speculatively steer an indirect branch
[all …]
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq_cmd.h285 /* command structures and indirect data structures */
289 * - _data for indirect sent data
290 * - _resp for indirect return data (data which is both will use _data)
325 /* Send driver version (indirect 0x0002) */
368 /* Get function capabilities (indirect 0x000A)
369 * Get device capabilities (indirect 0x000B)
437 /* Set ARP Proxy command / response (indirect 0x0104) */
449 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
476 /* Manage MAC Address Read Command (indirect 0x0107) */
556 /* Used by many indirect commands that only pass an seid and a buffer in the
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/openbmc/linux/sound/mips/
H A Dhal2.h13 /* Indirect status register */
28 /* Indirect address register */
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
44 /* blockin which the indirect */
71 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
72 * Indirect Data registers. Write the address to the Indirect Address register
78 * When we write to indirect registers which are larger than one word (16 bit)
79 * we have to fill more than one indirect register before writing. When we read
[all …]
/openbmc/linux/fs/sysv/
H A Ditree.c5 * Handling of indirect blocks' trees.
14 enum {DIRECT = 10, DEPTH = 4}; /* Have triple indirect */
63 } Indirect; typedef
67 static inline void add_chain(Indirect *p, struct buffer_head *bh, sysv_zone_t *v) in add_chain()
73 static inline int verify_chain(Indirect *from, Indirect *to) in verify_chain()
85 static Indirect *get_branch(struct inode *inode, in get_branch()
88 Indirect chain[], in get_branch()
92 Indirect *p = chain; in get_branch()
128 Indirect *branch) in alloc_branch()
173 Indirect chain[], in splice_branch()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c58 int inst_idx, bool indirect);
415 * @indirect: indirectly write sram
419 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
429 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
433 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
437 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
439 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
442 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
444 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
446 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_5.c469 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
476 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
482 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
487 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
491 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_0.c387 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) in vcn_v2_0_mc_resume_dpg_mode() argument
394 if (!indirect) { in vcn_v2_0_mc_resume_dpg_mode()
397 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
400 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
402 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
405 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
407 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
409 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
415 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
418 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v4_0.c432 * @indirect: indirectly write sram
436 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
445 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
448 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
451 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
453 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
456 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
458 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
460 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v3_0.c498 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
505 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
508 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
511 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
513 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
529 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_adminq_cmd.h36 /* Send driver version (indirect 0x0002) */
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
139 /* Manage MAC address, read command - indirect (0x0107)
245 * Get Resource Allocation command (indirect 0x0204)
246 * Allocate Resources command (indirect 0x0208)
247 * Free Resources command (indirect 0x0209)
248 * Get Allocated Resource Descriptors Command (indirect 0x020A)
249 * Share Resource command (indirect 0x020B)
272 /* Allocate Resources command (indirect 0x0208)
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dioapic.h17 /* Indirect addressed register offset */
24 * This routine reads I/O APIC indirect addressed register.
26 * @reg: address of indirect addressed register
34 * This routine writes I/O APIC indirect addressed register.
36 * @reg: address of indirect addressed register
/openbmc/linux/arch/x86/kernel/
H A Dksysfs.c95 struct setup_indirect *indirect; in get_setup_data_size() local
114 indirect = (struct setup_indirect *)data->data; in get_setup_data_size()
116 if (indirect->type != SETUP_INDIRECT) in get_setup_data_size()
117 *size = indirect->len; in get_setup_data_size()
138 struct setup_indirect *indirect; in type_show() local
162 indirect = (struct setup_indirect *)data->data; in type_show()
164 ret = sprintf(buf, "0x%x\n", indirect->type); in type_show()
179 struct setup_indirect *indirect; in setup_data_data_read() local
203 indirect = (struct setup_indirect *)data->data; in setup_data_data_read()
205 if (indirect->type != SETUP_INDIRECT) { in setup_data_data_read()
[all …]
H A Dkdebugfs.c49 /* Is it direct data or invalid indirect one? */ in setup_data_read()
91 struct setup_indirect *indirect; in create_setup_data_nodes() local
129 indirect = (struct setup_indirect *)data->data; in create_setup_data_nodes()
131 if (indirect->type != SETUP_INDIRECT) { in create_setup_data_nodes()
132 node->paddr = indirect->addr; in create_setup_data_nodes()
133 node->type = indirect->type; in create_setup_data_nodes()
134 node->len = indirect->len; in create_setup_data_nodes()
/openbmc/linux/arch/m68k/math-emu/
H A Dfp_decode.h29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * a0 - will point to source/dest operand for any indirect mode
121 | .long "addr register indirect"
122 | .long "addr register indirect postincrement"
123 | .long "addr register indirect predecrement"
184 | .long "no memory indirect action/reserved","null outer displacement"
196 | test if %pc is the base register for the indirect addr mode
220 | addressing mode: address register indirect
244 | addressing mode: address register indirect with postincrement
263 | addressing mode: address register indirect with predecrement
[all …]
/openbmc/linux/fs/ext2/
H A Dinode.c118 } Indirect; typedef
120 static inline void add_chain(Indirect *p, struct buffer_head *bh, __le32 *v) in add_chain()
126 static inline int verify_chain(Indirect *from, Indirect *to) in verify_chain()
139 * followed (on disk) by an indirect block.
142 * data blocks at leaves and indirect blocks in intermediate nodes.
149 * we need to know is the capacity of indirect blocks (taken from the
155 * indirect block) is spelled differently, because otherwise on an
206 * ext2_get_branch - read the chain of indirect blocks leading to data
209 * @offsets: offsets of pointers in inode/indirect blocks
219 * for i>0) and chain[i].bh points to the buffer_head of i-th indirect
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A Dpipeline.json7 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
15 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
24 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
33 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
38 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
42 …indirect CALL branch instructions retired. Branch prediction predicts the branch target and enabl…
51 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
56 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct…
60 …indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the b…
69 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dbranch.json10 …"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a pr…
55 …"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each…
60 "BriefDescription": "Retired indirect branch instructions."
75 "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."

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