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/openbmc/linux/drivers/clocksource/
H A Dtimer-microchip-pit64b.c54 * @gclk: PIT64B's generic clock
60 struct clk *gclk; member
139 clk_disable_unprepare(timer->gclk); in mchp_pit64b_suspend()
147 clk_prepare_enable(timer->gclk); in mchp_pit64b_resume()
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
266 * This function, first tries to use GCLK by requesting the desired rate from
268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
278 * | |-->gclk -->|-->| | +---------+ +-----+ |
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/openbmc/linux/sound/soc/atmel/
H A Dmchp-spdifrx.c296 * @gclk: generic clock
306 struct clk *gclk; member
476 /* GCLK is enabled by runtime PM. */ in mchp_spdifrx_hw_params()
477 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_params()
479 ret = clk_set_min_rate(dev->gclk, params_rate(params) * in mchp_spdifrx_hw_params()
483 "unable to set gclk min rate: rate %u * ratio %u + 1\n", in mchp_spdifrx_hw_params()
486 clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
489 ret = clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
491 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdifrx_hw_params()
495 dev_dbg(dev->dev, "GCLK range min set to %d\n", in mchp_spdifrx_hw_params()
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H A Dmchp-spdiftx.c196 struct clk *gclk; member
485 /* GCLK is enabled by runtime PM. */ in mchp_spdiftx_hw_params()
486 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_params()
488 ret = clk_set_rate(dev->gclk, params_rate(params) * in mchp_spdiftx_hw_params()
492 "unable to change gclk rate to: rate %u * ratio %u\n", in mchp_spdiftx_hw_params()
496 ret = clk_prepare_enable(dev->gclk); in mchp_spdiftx_hw_params()
498 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdiftx_hw_params()
502 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, in mchp_spdiftx_hw_params()
738 clk_disable_unprepare(spdiftx->gclk); in mchp_spdiftx_runtime_suspend()
755 ret = clk_prepare_enable(spdiftx->gclk); in mchp_spdiftx_runtime_resume()
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H A Dmchp-i2s-mcc.c242 struct clk *gclk; member
447 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
451 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
455 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
483 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
491 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
702 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
705 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
710 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
712 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
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H A Datmel-classd.c31 struct clk *gclk; member
130 err = clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_startup()
365 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_hw_params()
367 ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate); in atmel_classd_cpu_dai_hw_params()
377 return clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_hw_params()
387 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_shutdown()
552 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_classd_probe()
553 if (IS_ERR(dd->gclk)) { in atmel_classd_probe()
554 ret = PTR_ERR(dd->gclk); in atmel_classd_probe()
H A Datmel-i2s.c200 struct clk *gclk; member
298 if (!dev->gclk) { in atmel_i2s_get_gck_param()
445 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
455 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
459 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
580 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
594 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
665 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
666 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
667 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
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H A Datmel-pdmic.c31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
527 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
602 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
603 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
604 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
609 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
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H A Dmchp-pdmc.c111 struct clk *gclk; member
582 round_rate = clk_round_rate(dd->gclk, in mchp_pdmc_hw_params()
599 clk_disable_unprepare(dd->gclk); in mchp_pdmc_hw_params()
602 ret = clk_set_rate(dd->gclk, gclk_rate); in mchp_pdmc_hw_params()
603 clk_prepare_enable(dd->gclk); in mchp_pdmc_hw_params()
605 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", in mchp_pdmc_hw_params()
985 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_suspend()
1002 ret = clk_prepare_enable(dd->gclk); in mchp_pdmc_runtime_resume()
1014 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_resume()
1052 dd->gclk = devm_clk_get(dev, "gclk"); in mchp_pdmc_probe()
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/openbmc/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
/openbmc/linux/drivers/pwm/
H A Dpwm-atmel-tcb.c56 struct clk *gclk; member
276 * If there is a gclk, the first divisor is actually the gclk selector in atmel_tcb_pwm_config()
278 if (tcbpwmc->gclk) in atmel_tcb_pwm_config()
431 tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk"); in atmel_tcb_pwm_probe()
432 if (IS_ERR(tcbpwm->gclk)) { in atmel_tcb_pwm_probe()
433 err = PTR_ERR(tcbpwm->gclk); in atmel_tcb_pwm_probe()
462 clk_put(tcbpwm->gclk); in atmel_tcb_pwm_probe()
480 clk_put(tcbpwm->gclk); in atmel_tcb_pwm_remove()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Datmel,sama5d2-i2s.yaml34 with gclk when Master Mode is required.
40 - const: gclk
82 clock-names = "pclk", "gclk", "muxclk";
H A Dmicrochip,sama7g5-spdifrx.yaml37 - const: gclk
72 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-spdiftx.yaml40 - const: gclk
75 clock-names = "pclk", "gclk";
H A Datmel,sama5d2-pdmic.yaml36 - const: gclk
91 clock-names = "pclk", "gclk";
H A Datmel,sama5d2-classd.yaml41 - const: gclk
93 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-pdmc.yaml40 - const: gclk
100 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-i2smcc.yaml47 - const: gclk
107 clock-names = "pclk", "gclk";
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-clocks.dtsi351 l3_gclk: clock-l3-gclk {
360 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
468 l4_rtc_gclk: clock-l4-rtc-gclk {
477 l4hs_gclk: clock-l4hs-gclk {
486 l3s_gclk: clock-l3s-gclk {
495 l4fw_gclk: clock-l4fw-gclk {
504 l4ls_gclk: clock-l4ls-gclk {
522 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
547 lcd_gclk: clock-lcd-gclk@534 {
H A Dam43xx-clocks.dtsi424 pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
510 l3_gclk: clock-l3-gclk {
528 l4hs_gclk: clock-l4hs-gclk {
537 l3s_gclk: clock-l3s-gclk {
546 l4ls_gclk: clock-l4ls-gclk {
555 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi344 clock-names = "pclk", "gclk";
359 clock-names = "pclk", "gclk";
587 clock-names = "pclk", "gclk";
599 clock-names = "pclk", "gclk";
611 clock-names = "pclk", "gclk";
623 clock-names = "pclk", "gclk";
634 clock-names = "pclk", "gclk";
646 clock-names = "pclk", "gclk";
668 clock-names = "pclk", "gclk";
676 clock-names = "pclk", "gclk";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,emev2-smu.yaml81 const: renesas,emev2-smu-gclk
135 compatible = "renesas,emev2-smu-gclk";
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c149 int gclk = cstate->domain[nv_clk_src_core]; in nv40_clk_calc() local
155 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, in nv40_clk_calc()
169 if (sclk && sclk != gclk) { in nv40_clk_calc()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dspeed.c24 * If for some reason measuring the gclk frequency won't in get_clocks()
/openbmc/u-boot/drivers/clk/at91/
H A DKconfig55 clock is the generic clock (GCLK) and is managed by
/openbmc/linux/drivers/tty/serial/
H A Datmel_serial.c113 struct clk *gclk; /* uart generic clock */ member
2110 if (__clk_is_enabled(atmel_port->gclk)) in atmel_serial_pm()
2111 clk_disable_unprepare(atmel_port->gclk); in atmel_serial_pm()
2305 * if we use the GCLK as the clock source driving the baudrate in atmel_set_termios()
2309 if (__clk_is_enabled(atmel_port->gclk)) in atmel_set_termios()
2310 clk_disable_unprepare(atmel_port->gclk); in atmel_set_termios()
2311 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2315 clk_set_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2316 ret = clk_prepare_enable(atmel_port->gclk); in atmel_set_termios()
2328 * Set the Clock Divisor for GCLK to 1. in atmel_set_termios()
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