Lines Matching full:gclk
113 struct clk *gclk; /* uart generic clock */ member
2110 if (__clk_is_enabled(atmel_port->gclk)) in atmel_serial_pm()
2111 clk_disable_unprepare(atmel_port->gclk); in atmel_serial_pm()
2305 * if we use the GCLK as the clock source driving the baudrate in atmel_set_termios()
2309 if (__clk_is_enabled(atmel_port->gclk)) in atmel_set_termios()
2310 clk_disable_unprepare(atmel_port->gclk); in atmel_set_termios()
2311 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2315 clk_set_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2316 ret = clk_prepare_enable(atmel_port->gclk); in atmel_set_termios()
2328 * Set the Clock Divisor for GCLK to 1. in atmel_set_termios()
2930 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); in atmel_serial_probe()
2931 if (IS_ERR(atmel_port->gclk)) { in atmel_serial_probe()
2932 ret = PTR_ERR(atmel_port->gclk); in atmel_serial_probe()