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/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-apac-viewcomp.c1 // SPDX-License-Identifier: GPL-2.0+
2 // apac-viewcomp.h - Keytable for apac_viewcomp Remote Controller
4 // keymap imported from ir-keymaps.c
8 #include <media/rc-map.h>
49 { 0x0c, KEY_KPPLUS }, /* fine tune >>>> */
50 { 0x18, KEY_KPMINUS }, /* fine tune <<<< */
H A Drc-winfast.c1 // SPDX-License-Identifier: GPL-2.0+
2 // winfast.h - Keytable for winfast Remote Controller
4 // keymap imported from ir-keymaps.c
8 #include <media/rc-map.h>
11 /* Table for Leadtek Winfast Remote Controls - used by both bttv and cx88 */
44 { 0x18, KEY_KPPLUS }, /* fine tune + , not on Y040052 */
45 { 0x19, KEY_KPMINUS }, /* fine tune - , not on Y040052 */
70 { 0x3a, KEY_VOLUMEDOWN }, /* MCE -VOL, on Y04G0033 */
72 { 0x3f, KEY_CHANNELDOWN } /* MCE -CH, on Y04G0033 */
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
63 while (len-- > 0) { in __rtl_writephy_batch()
64 __phy_write(phydev, regs->reg, regs->val); in __rtl_writephy_batch()
479 * Fine Tune Switching regulator parameter in rtl8168d_1_hw_phy_config()
497 /* Fine tune PLL performance */ in rtl8168d_1_hw_phy_config()
518 /* Fine tune PLL performance */ in rtl8168d_2_hw_phy_config()
542 /* Channel estimation fine tune */ in rtl8168e_1_hw_phy_config()
591 /* Channel estimation fine tune */ in rtl8168e_2_hw_phy_config()
599 /* For 4-corner performance improve */ in rtl8168e_2_hw_phy_config()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 has a configurable arbitration algorithm to allow the user to fine-tune
27 const: nvidia,tegra20-mc-gart
31 - description: controller registers
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/openbmc/linux/arch/powerpc/platforms/ps3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 defaults should be fine for most users, but these options may make
42 This option is only for experts who may have the desire to fine
43 tune the pagetable size on their system. The value here is
126 tristate "PS3 BD/DVD/CD-ROM Storage Driver"
132 This support is required to access the PS3 BD/DVD/CD-ROM drive.
/openbmc/openbmc/poky/documentation/migration-guides/
H A Dmigration-3.4.rst1 .. SPDX-License-Identifier: CC-BY-SA-2.0-UK
4 ----------------------------------
27 SRC_URI_remove_qemux86-64 = "file://somefile3"
29 FILES_${PN}-ptest = "${bindir}/xyz"
31 BASE_LIB_tune-cortexa76 = "lib"
32 SRCREV_pn-bash = "abc"
33 BB_TASK_NICE_LEVEL_task-testimage = '0'
39 SRC_URI:remove:qemux86-64 = "file://somefile3"
41 FILES:${PN}-ptest = "${bindir}/xyz"
43 BASE_LIB:tune-cortexa76 = "lib"
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/openbmc/u-boot/drivers/ram/aspeed/
H A DKconfig126 to fine-tune the write DQ/DQS alignment. Please don't change it if you
/openbmc/linux/drivers/base/firmware_loader/
H A Dsysfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * struct firmware_fallback_config - firmware fallback configuration settings
18 * Helps describe and fine tune the fallback mechanism.
89 struct fw_priv *fw_priv = fw_sysfs->fw_priv; in fw_load_abort()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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/openbmc/u-boot/board/ccv/xpress/
H A Dimximage.cfg1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
5 * Refer doc/README.imximage for more details about how-to configure
25 * Addr-type Address Value
28 * Addr-type register length (1,2 or 4 bytes)
58 DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
81 * Device Part Number: IME1G16D3EEBG-15EI
96 DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
100 * For target board, may need to run write leveling calibration to fine tune
125 /* Clock Fine Tuning */
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
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/openbmc/linux/drivers/slimbus/
H A Dsched.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
10 * slim_ctrl_clk_pause() - Called by slimbus controller to enter/exit
17 * Slimbus specification needs this sequence to turn-off clocks for the bus.
20 * To exit clock-pause, controller typically wakes up active framer device.
23 * For entering clock-pause, -EBUSY is returned if a message txn in pending.
29 struct slim_sched *sched = &ctrl->sched; in slim_ctrl_clk_pause()
36 return -EINVAL; in slim_ctrl_clk_pause()
38 mutex_lock(&sched->m_reconf); in slim_ctrl_clk_pause()
40 if (sched->clk_state == SLIM_CLK_ACTIVE) { in slim_ctrl_clk_pause()
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/openbmc/openbmc/meta-arm/meta-arm/recipes-security/trusted-services/
H A Dtrusted-services-src.inc3 LICENSE = "Apache-2.0 & BSD-3-Clause & BSD-2-Clause & Zlib"
5 …it.trustedfirmware.org/TS/trusted-services.git;protocol=https;branch=main;name=trusted-services;de…
11 file://0001-Allow-configuring-flash-image-files-compile-time.patch \
15 SRCREV_trusted-services = "602be607198ea784bc5ab1c0c9d3ac4e2c67f1d9"
18 S = "${WORKDIR}/git/trusted-services"
31 # Nanopb, tag "nanopb-0.4.7" plus some further fixes
51 SRCREV_FORMAT = "trusted-services_dtc_mbedtls_nanopb_qcbor_tcose_cpputest"
66 # Fine tune MbedTLS configuration for crypto only operation.
67 sh -c "cd ${WORKDIR}/git/mbedtls; python3 scripts/config.py crypto"
71 EXTRA_OECMAKE += "-DDTC_SOURCE_DIR=${WORKDIR}/git/dtc \
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/openbmc/u-boot/board/olimex/mx23_olinuxino/
H A Dspl_boot.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/iomux-mx23.h>
12 #include <asm/arch/imx-regs.h>
92 /* Fine-tune the DRAM configuration. */
/openbmc/u-boot/include/
H A Dnetdev.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * netdev.h - definitions an prototypes for network devices
15 * Board and CPU-specific initialization functions
20 * -1: failure
124 * Allow FEC to fine-tune MII configuration on boards which require this.
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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/openbmc/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
66 writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); in phy_usb3_mode_set()
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/openbmc/openbmc/meta-security/recipes-scanners/clamav/files/
H A Dclamav-milter.conf.sample2 ## Example config file for clamav-milter
15 # [[unix|local]:]/path/to/file - to specify a unix domain socket
16 # inet:port@[hostname|ip-address] - to specify an ipv4 socket
17 # inet6:port@[hostname|ip-address] - to specify an ipv6 socket
20 #MilterSocket /tmp/clamav-milter.socket
36 # Run as another user (clamav-milter must be started by root for this option to work)
41 # Initialize supplementary group access (clamav-milter must be started by root).
67 #PidFile /var/run/clamav/clamav-milter.pid
90 # with the same socket: clamd servers will be selected in a round-robin fashion.
103 # To specify a locally orignated, non-smtp, email use the keyword "local"
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/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt3 STM32 ADC is a successive approximation analog-to-digital converter.
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
27 "st,stm32mp1-adc-core"
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/openbmc/qemu/.gitlab-ci.d/
H A Dbase.yml8 # For purposes of CI rules, upstream is the gitlab.com/qemu-project
11 QEMU_CI_UPSTREAM: qemu-project
19 # For pipelines running for stable "staging-X.Y" branches
28 # we don't need. The --filter options avoid blobs and tree references we aren't going to use
30 GIT_FETCH_EXTRA_FLAGS: --filter=blob:none --filter=tree:0 --no-tags --prune --quiet
41 - if: '$CI_PROJECT_NAMESPACE == $QEMU_CI_UPSTREAM && $CI_COMMIT_BRANCH =~ /^stable-/'
45 - if: '$CI_PROJECT_NAMESPACE == $QEMU_CI_UPSTREAM && $CI_COMMIT_TAG'
49 - if: '$CI_PROJECT_NAMESPACE == $QEMU_CI_UPSTREAM && $CI_PIPELINE_SOURCE == "schedule"'
53 - if: '$QEMU_JOB_CIRRUS && ($CIRRUS_GITHUB_REPO == null || $CIRRUS_API_TOKEN == null)'
57 …- if: '$QEMU_JOB_PUBLISH == "1" && $CI_PROJECT_NAMESPACE == $QEMU_CI_UPSTREAM && $CI_COMMIT_BRANCH…
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/openbmc/linux/include/drm/
H A Ddrm_mm.h3 * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA.
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
60 * enum drm_mm_insert_mode - control search and allocation behaviour
118 * Only check the first hole for suitablity and report -ENOSPC
129 * insert the node at the top of the hole or report -ENOSPC if
140 * insert the node at the bottom of the hole or report -ENOSPC if
149 * struct drm_mm_node - allocated block in the DRM allocator
152 * pre-reserved nodes inserted using drm_mm_reserve_node() the structure is
158 /** @color: Opaque driver-private tag. */
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/openbmc/u-boot/drivers/video/
H A Dmxsfb.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
11 #include <asm/arch/imx-regs.h>
17 #include <asm/mach-imx/dma.h>
27 * mxsfb_system_setup() - Fine-tune LCDIF configuration
30 * needed when driving the controller in System-Mode to operate an 8080 or
57 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); in mxs_lcd_init()
60 mxs_reset_block(&regs->hw_lcdif_ctrl_reg); in mxs_lcd_init()
87 &regs->hw_lcdif_ctrl); in mxs_lcd_init()
90 &regs->hw_lcdif_ctrl1); in mxs_lcd_init()
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/openbmc/linux/drivers/iio/light/
H A Dacpi-als.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (C) 2012-2013 Martin Liska <marxin.liska@gmail.com>
12 * Copyright (C) 2013-2014 Marek Vasut <marex@denx.de>
29 #define ACPI_ALS_DEVICE_NAME "acpi-als"
73 * The _ALR property returns tables that can be used to fine-tune the values
90 status = acpi_evaluate_integer(als->device->handle, prop, NULL, in acpi_als_read_value()
94 acpi_evaluation_failure_warn(als->device->handle, prop, status); in acpi_als_read_value()
95 return -EIO; in acpi_als_read_value()
111 iio_trigger_poll_nested(als->trig); in acpi_als_notify()
115 dev_dbg(&device->dev, in acpi_als_notify()
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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
68 struct i2c_adapter *adap = client->adapter; in ps8622_set()
72 msg.addr = client->addr + page; in ps8622_set()
80 client->addr + page, reg, val, ret); in ps8622_set()
86 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
110 * [3:2] CDR tune wait cycle before measure for fine tune in ps8622_send_config()
137 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
147 /* Gitune=-37% */ in ps8622_send_config()
167 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
179 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
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