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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12 |
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dbac4009 |
| 21-Sep-2022 |
Joel Stanley <joel@jms.id.au> |
ram/aspeed: Remove ECC config option
Always build the code now that it is enabled by device tree.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: ht
ram/aspeed: Remove ECC config option
Always build the code now that it is enabled by device tree.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220921074439.2265651-3-joel@jms.id.au
Change-Id: I98fdc3a7a09347624ec73f03819003f34cb39a30
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058de9e5 |
| 05-Oct-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: aspeed: DDR4 DRAM and PHY ODT/Ron options depend on AST2600
Only AST2600 DRAM driver supports DDR4 DRAM and PHY ODT/Ron adjustment.
So let these options depend on CONFIG_ASPEED_AST2600.
Signed
ram: aspeed: DDR4 DRAM and PHY ODT/Ron options depend on AST2600
Only AST2600 DRAM driver supports DDR4 DRAM and PHY ODT/Ron adjustment.
So let these options depend on CONFIG_ASPEED_AST2600.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Id4449c6703773dcc9585cab8f27b71c027ad6579
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23bcb5d2 |
| 25-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for DRAM ODT 80 ohm
Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.
ram: ast2600: add option for DRAM ODT 80 ohm
Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I8a0775309fac689a607ed4a3077b9eded61d8828
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16261a32 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Revert "Revert "ram: ast2600: add option for write data eye training result offset""
This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.
Reason for revert: rebase dram driver
Change-Id:
Revert "Revert "ram: ast2600: add option for write data eye training result offset""
This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.
Reason for revert: rebase dram driver
Change-Id: If9644975969922093d6be6d32f30303e4b165d07
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26026662 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Revert "ram: ast2600: add option for write data eye training result offset"
This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.
Reason for revert: rebase sdram_ast2600 driver
Change-Id:
Revert "ram: ast2600: add option for write data eye training result offset"
This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.
Reason for revert: rebase sdram_ast2600 driver
Change-Id: Ic6ada37982099c7f0750cffd862c65ff29fef9a5
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841e0804 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for write data eye training result offset
Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.
Signed-off-by: Dylan Hung <dylan
ram: ast2600: add option for write data eye training result offset
Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: If95fc958267ce18e85d686f3f33fe0858cdc532b
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323f39fb |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: use macro to represent DRAM MR
Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both
ram: ast2600: use macro to represent DRAM MR
Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both side.
Also, this commit modifies the default RTT and RON setting
RTT_WR: disable
RTT_NOM: 48 ohm
RTT_PARK: 48 ohm
DRAM output driver impedance: 34 ohm
PHY Ron: 34 ohm
PHY ODT: 80 ohm
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38be1ef106a914dcfb5da3149ff59ca6ec4f3fbb
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cb2cc580 |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option to configure DRAM output impedance
The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.
Signed-off-by: Dylan Hung <dylan_hung@aspe
ram: ast2600: add option to configure DRAM output impedance
The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I0f2c5e9bd196a2dbb81e5a8a588f33079340a7ae
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dd3a6e11 |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for PHY ODT 80 ohm
Add option to select PHY ODT 80 ohm
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ia0e862de4f223e675414428abe1cc0cfeea8a1b9
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Revision tags: v00.04.11 |
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b415f713 |
| 17-May-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: aspeed: add AST2600 ODT configuration
PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)
DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101
ram: aspeed: add AST2600 ODT configuration
PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)
DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101 = 48 ohm
- b'011 = 40 ohm (default)
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38883cbdd6de5a0f042573506c88a10f16d14f83
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Revision tags: v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01 |
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c3d7eb06 |
| 19-Jul-2021 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: aspeed: specify the DDR4 speed configs for AST2600
only AST2600 supports DDR4 speed selection
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ibf140e512c968eb378f8303432c79b31
ram: aspeed: specify the DDR4 speed configs for AST2600
only AST2600 supports DDR4 speed selection
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ibf140e512c968eb378f8303432c79b31fd166710
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Revision tags: v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04 |
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2f82724a |
| 15-Jan-2020 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
Merge branch 'feature/palladium' into aspeed-dev-v2019.04
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cff1d497 |
| 15-Jan-2020 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
ast2600: Add palladium support
Make CONFIG_ASPEED_PALLADIUM globally supported to build
binary for the simulation purposes on AST2600.
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Revision tags: v2020.01 |
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a659db20 |
| 24-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'ddr1333' into aspeed-dev-v2019.04
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fd8b1ad3 |
| 24-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
add ddr1333 config
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27b58130 |
| 11-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'bypass-dramtest' into aspeed-dev-v2019.04
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23156602 |
| 11-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
add ASPEED_BYPASS_SELFTEST to bypass dram BIST
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e87eb270 |
| 05-Dec-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Merge branch 'aspeed-dev-v2019.04' into aspeed-master-v2019.04
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e109c27b |
| 02-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'revise_ecc' into aspeed-dev-v2019.04
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cbb11045 |
| 02-Dec-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
revise ECC size configuration and calculation
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5e3d9658 |
| 02-Dec-2019 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
Merge branch 'bugfix/ram_config' into aspeed-dev-v2019.04
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92a5848d |
| 02-Dec-2019 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
config: aspeed: Fix RAM selection
The Aspeed RAM-related configurations should 'depends on'
the top-level CONFIG_RAM instead of 'select' in Kconfig.
The CONFIG_RAM and CONFIG_SPL_RAM is also added
config: aspeed: Fix RAM selection
The Aspeed RAM-related configurations should 'depends on'
the top-level CONFIG_RAM instead of 'select' in Kconfig.
The CONFIG_RAM and CONFIG_SPL_RAM is also added in Aspeed
default configuration to enable RAM support.
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35cf0015 |
| 17-Nov-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'fix_ram_kconfig' into aspeed-dev-v2019.04
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b9fa99a0 |
| 17-Nov-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
add an newline at the EOF to avoid build error
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Revision tags: v2019.10, v00.02.05, v00.02.04, v00.02.03 |
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baa782ec |
| 09-Sep-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'debug/ddr4_100' into aspeed-dev-v2019.04
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