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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-epp.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
15 pattern: "^epp@[0-9a-f]+$"
19 - nvidia,tegra20-epp
20 - nvidia,tegra30-epp
21 - nvidia,tegra114-epp
38 - const: epp
62 epp@540c0000 {
63 compatible = "nvidia,tegra20-epp";
68 reset-names = "epp";
/openbmc/linux/drivers/scsi/
H A Dppa.h18 * to support EPP and scatter-gather. [0.26-athena]
22 * Fixed EPP to handle "software" changing of EPP port data direction.
23 * Chased down EPP timeouts
32 * Fixed id_probe for EPP 1.9 chipsets (misdetected as EPP 1.7)
38 * Hack and slash at the init code (EPP device check routine)
98 #define PPA_EPP_8 3 /* EPP mode, 8 bit */
99 #define PPA_EPP_16 4 /* EPP mode, 16 bit */
100 #define PPA_EPP_32 5 /* EPP mode, 32 bit */
108 "EPP 8 bit",
109 "EPP 16 bit",
[all …]
H A Dimm.h37 * Now have byte mode working (only EPP and ECP to go now... :=)
40 * Thirty minutes of further coding results in EPP working on my machine.
91 #define IMM_EPP_8 3 /* EPP mode, 8 bit */
92 #define IMM_EPP_16 4 /* EPP mode, 16 bit */
93 #define IMM_EPP_32 5 /* EPP mode, 32 bit */
101 [IMM_EPP_8] = "EPP 8 bit",
102 [IMM_EPP_16] = "EPP 16 bit",
104 [IMM_EPP_32] = "EPP 16 bit",
106 [IMM_EPP_32] = "EPP 32 bit",
/openbmc/linux/tools/power/cpupower/utils/
H A Dcpupower-set.c21 {"epp", required_argument, NULL, 'e'},
43 int epp:1; in cmd_set() member
51 char epp[30], mode[20]; in cmd_set() local
80 if (params.epp) in cmd_set()
82 if (sscanf(optarg, "%29s", epp) != 1) { in cmd_set()
86 params.epp = 1; in cmd_set()
157 if (params.epp) { in cmd_set()
158 ret = cpupower_set_epp(cpu, epp); in cmd_set()
161 "Error setting epp value on CPU %d\n", cpu); in cmd_set()
/openbmc/linux/drivers/cpufreq/
H A Damd-pstate.c73 * AMD Energy Preference Performance (EPP)
74 * The EPP is used in the CCLK DPM controller to drive
76 * short periods of activity. EPP values will be utilized for
78 * display strings corresponding to EPP index in the
131 u64 epp; in amd_pstate_get_epp() local
136 epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, in amd_pstate_get_epp()
138 if (epp) in amd_pstate_get_epp()
139 return epp; in amd_pstate_get_epp()
141 epp = (cppc_req_cached >> 24) & 0xFF; in amd_pstate_get_epp()
143 ret = cppc_get_epp_perf(cpudata->cpu, &epp); in amd_pstate_get_epp()
[all …]
H A Dintel_pstate.c212 * (EPP) or energy performance bias (EPB),
214 * @epp_policy: Last saved policy used to set EPP/EPB
633 s16 epp; in intel_pstate_get_epp() local
638 * MSR_HWP_REQUEST, so need to read and get EPP. in intel_pstate_get_epp()
641 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, in intel_pstate_get_epp()
643 if (epp) in intel_pstate_get_epp()
644 return epp; in intel_pstate_get_epp()
646 epp = (hwp_req_data >> 24) & 0xff; in intel_pstate_get_epp()
648 /* When there is no EPP present, HWP uses EPB settings */ in intel_pstate_get_epp()
649 epp = intel_pstate_get_epb(cpu_data); in intel_pstate_get_epp()
[all …]
/openbmc/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.814 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
46 Energy_Performance_Preference (EPP) field in
109 VALUE STRING EPB EPP
122 \fB-a, --all value-string\fP Sets all EPB and EPP and HWP limit fields to the value associated with
133 \fB-P, --hwp-epp\fP set HWP.EPP per-core or per-package.
185 cpu0: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
188 cpu1: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
191 cpu2: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
194 cpu3: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
/openbmc/linux/include/uapi/linux/
H A Dparport.h58 #define PARPORT_MODE_EPP (1<<2) /* Hardware EPP. */
65 Nibble mode, byte mode, ECP, ECPRLE and EPP are their own
76 #define IEEE1284_MODE_EPPSL (1<<11) /* EPP 1.7 */
93 #define PARPORT_EPP_FAST_32 PARPORT_EPP_FAST /* 32-bit EPP transfers */
94 #define PARPORT_EPP_FAST_16 (1<<2) /* 16-bit EPP transfers */
95 #define PARPORT_EPP_FAST_8 (1<<3) /* 8-bit EPP transfers */
/openbmc/linux/arch/sparc/include/asm/
H A Dns87303.h40 #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
41 #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
46 #define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
50 #define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
58 #define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
/openbmc/qemu/hw/char/
H A Dparallel.c63 #define PARA_STS_TMOUT 0x01 /* EPP timeout */
171 /* Controls not correct for EPP address cycle, so do nothing */ in parallel_ioport_write_hw()
186 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_write_hw()
211 trace_parallel_ioport_write("EPP", addr, val); in parallel_ioport_eppdata_write_hw2()
213 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw2()
236 trace_parallel_ioport_write("EPP", addr, val); in parallel_ioport_eppdata_write_hw4()
238 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw4()
326 /* Controls not correct for EPP addr cycle, so do nothing */ in parallel_ioport_read_hw()
342 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_read_hw()
371 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw2()
[all …]
/openbmc/linux/drivers/ata/pata_parport/
H A Ddstr.c21 * 2 8-bit EPP mode
22 * 3 EPP-16
23 * 4 EPP-32
209 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in dstr_log_adapter()
H A Depia.c25 * 3 8-bit EPP mode
26 * 4 16-bit EPP
27 * 5 32-bit EPP
99 * some EPP counters ... currently we know about 3 different block
284 char *mode[6] = { "4-bit", "5/3", "8-bit", "EPP-8", "EPP-16", "EPP-32"}; in epia_log_adapter()
H A Dbpck6.c328 /* EPP */ in bpck6_open()
357 /* EPP */ in bpck6_deselect()
401 return 5; /* Can do EPP */ in bpck6_test_port()
436 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in bpck6_log_adapter()
447 .epp_first = 2, /* 2-5 use epp (need 8 ports) */
H A Dcomm.c22 * 2 8-bit EPP mode
179 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in comm_log_adapter()
H A Don26.c21 * 2 8-bit EPP mode
22 * 3 EPP-16
23 * 4 EPP-32
288 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in on26_log_adapter()
H A Dfrpw.c270 char *mode[6] = { "4-bit", "8-bit", "EPP", "EPP-8", "EPP-16", "EPP-32"}; in frpw_log_adapter()
H A Dbpck.c284 /* This fakes the EPP protocol to turn off EPP ... */ in bpck_force_spp()
474 char *mode_str[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in bpck_log_adapter()
H A Depat.c253 /* Request EPP */ in epat_connect()
318 { "4-bit", "5/3", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in epat_log_adapter()
/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Dsiena_sriov.c406 struct efx_endpoint_page *epp; in __efx_siena_sriov_push_vf_status() local
438 list_for_each_entry(epp, &nic_data->local_page_list, link) { in __efx_siena_sriov_push_vf_status()
447 copy[pos].from_addr = epp->addr; in __efx_siena_sriov_push_vf_status()
1087 struct efx_endpoint_page *epp; in efx_siena_sriov_peer_work() local
1126 epp = kmalloc(sizeof(*epp), GFP_KERNEL); in efx_siena_sriov_peer_work()
1127 if (!epp) in efx_siena_sriov_peer_work()
1129 epp->ptr = dma_alloc_coherent( in efx_siena_sriov_peer_work()
1131 &epp->addr, GFP_KERNEL); in efx_siena_sriov_peer_work()
1132 if (!epp->ptr) { in efx_siena_sriov_peer_work()
1133 kfree(epp); in efx_siena_sriov_peer_work()
[all …]
/openbmc/linux/drivers/parport/
H A Dieee1284_ops.c14 * Software emulated EPP fixes, Fred Barnes, 04/2001.
705 * EPP functions. *
708 /* EPP mode, forward channel, data. */
716 /* set EPP idle state (just to make sure) with strobe low */ in parport_ieee1284_epp_write_data()
752 /* EPP mode, reverse channel, data. */
760 /* set EPP idle state (just to make sure) with strobe high */ in parport_ieee1284_epp_read_data()
796 /* EPP mode, forward channel, addresses. */
804 /* set EPP idle state (just to make sure) with strobe low */ in parport_ieee1284_epp_write_addr()
840 /* EPP mode, reverse channel, addresses. */
848 /* Set EPP idle state (just to make sure) with strobe high */ in parport_ieee1284_epp_read_addr()
H A Dparport_pc.c31 * base+3 EPP address
32 * base+4 EPP data
204 * Clear TIMEOUT BIT in EPP MODE
300 /* EPP timeout should never occur... */ in parport_pc_epp_read_data()
301 … printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", in parport_pc_epp_read_data()
329 /* EPP timeout */ in parport_pc_epp_read_data()
974 "EPP and SPP", in show_parconfig_smsc37c669()
976 "ECP and EPP" }; in show_parconfig_smsc37c669()
1009 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n", in show_parconfig_smsc37c669()
1054 "EPP-1.9 and SPP", in show_parconfig_winbond()
[all …]
H A Dparport_ip32.c19 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
30 * EPP and ECP mode need to be tested. I currently do not own any
42 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
141 * @eppAddr: EPP Address Register
142 * @eppData0: EPP Data Register 0
143 * @eppData1: EPP Data Register 1
144 * @eppData2: EPP Data Register 2
145 * @eppData3: EPP Data Register 3
179 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */
327 "ECP", "EPP", "???", in parport_ip32_dump_state()
[all …]
H A Dparport_gsc.c47 * Clear TIMEOUT BIT in EPP MODE
138 * first clear an eventually pending EPP timeout in parport_SPP_supported()
140 * that does not even respond to SPP cycles if an EPP in parport_SPP_supported()
299 printmode(EPP); in parport_gsc_probe_port()
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt48 - epp: encoder pre-processor
51 - compatible: "nvidia,tegra<chip>-epp"
59 - epp
274 epp {
275 compatible = "nvidia,tegra20-epp";
280 reset-names = "epp";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.

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