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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
74 /* DP PHY swing and pre_emphasis tables */
85 struct phy *phy; member
87 void __iomem *edp; member
173 static int qcom_edp_phy_init(struct phy *phy) in qcom_edp_phy_init() argument
175 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_init() local
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm eDP PHY
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
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H A Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
22 "#phy-cells":
26 - compatible
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
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H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
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H A Dqcom,sc7280-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
20 const: qcom,sc7280-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sc8280xp-pmics.dtsi"
17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
26 compatible = "pwm-backlight";
28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
29 power-supply = <&vreg_edp_bl>;
31 pinctrl-names = "default";
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H A Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
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H A Dsc8280xp-lenovo-thinkpad-x13s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
132 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
133 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
146 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ in intel_dp_set_dpcd_sink_rates()
149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
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H A Dintel_bios.c55 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
88 return _get_blocksize(block_data - 3); in get_blocksize()
101 index += bdb->header_size; in find_raw_section()
102 total = bdb->bdb_size; in find_raw_section()
134 return block - bdb; in raw_block_offset()
149 list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) { in bdb_find_section()
150 if (entry->section_id == section_id) in bdb_find_section()
151 return entry->data + 3; in bdb_find_section()
209 if (ptrs->panel_name.table_size) in lfp_data_min_size()
210 size = max(size, ptrs->panel_name.offset + in lfp_data_min_size()
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/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dlink_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 /* eDP version 1.1 or lower */
45 /* eDP version 1.2 */
47 /* eDP version 1.3 */
76 /* TODO - factor lane_settings out because it changes during LT */
100 * training states - parameters that can change in link training
106 * a constant input pre-decided prior to link training.
124 /* phy test patterns*/
182 /* standard mode for eDP */
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
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/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
13 - Xinlei Lee <xinlei.lee@mediatek.com>
17 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
21 - $ref: /schemas/display/dsi-controller.yaml#
26 - enum:
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/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_parser.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
10 #include <linux/phy/phy.h>
11 #include <linux/phy/phy-dp.h>
52 * struct dp_display_data - display related device tree data.
55 * @phy_node: reference to phy device
69 * struct dp_ctrl_resource - controller's IO related data
72 * @phy_io: phy's mapped memory address
76 struct phy *phy; member
81 * struct dp_pinctrl - DP's pin control
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
28 force-hpd:
32 is used for some eDP screen which don not have a hpd signal.
34 hpd-gpios:
51 Port node with one endpoint connected to a dp-connector node.
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/openbmc/u-boot/arch/arm/dts/
H A Dsun50i-a64-pinebook.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sun50i-a64.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pwm/pwm.h>
18 compatible = "pine64,pinebook", "allwinner,sun50i-a64";
26 compatible = "regulator-fixed";
27 regulator-name = "bl-3v3";
28 regulator-min-microvolt = <3300000>;
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
12 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
19 compatible = "pwm-backlight";
20 brightness-levels = <
53 default-brightness-level = <200>;
57 edp_panel: edp-panel {
58 compatible = "lg,lp079qx1-sp0v";
60 enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
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/openbmc/linux/include/drm/display/
H A Ddrm_dp_helper.h75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 * @sdp_type: secondary-data packet type
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
166 /* DP/eDP DSC support */
176 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & in drm_dp_sink_supports_dsc()
183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | in drm_edp_dsc_sink_output_bpp()
184 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & in drm_edp_dsc_sink_output_bpp()
192 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * in drm_dp_dsc_sink_max_slice_width()
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/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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