1ced3aaeaSTaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ced3aaeaSTaniya Das%YAML 1.2 3ced3aaeaSTaniya Das--- 4ced3aaeaSTaniya Das$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml# 5ced3aaeaSTaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6ced3aaeaSTaniya Das 7ece3c319SKrzysztof Kozlowskititle: Qualcomm Display Clock & Reset Controller on SC7280 8ced3aaeaSTaniya Das 9ced3aaeaSTaniya Dasmaintainers: 10*60838878STaniya Das - Taniya Das <quic_tdas@quicinc.com> 11ced3aaeaSTaniya Das 12ced3aaeaSTaniya Dasdescription: | 13ece3c319SKrzysztof Kozlowski Qualcomm display clock control module provides the clocks, resets and power 14ece3c319SKrzysztof Kozlowski domains on SC7280. 15ced3aaeaSTaniya Das 16ece3c319SKrzysztof Kozlowski See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h 17ced3aaeaSTaniya Das 18ced3aaeaSTaniya Dasproperties: 19ced3aaeaSTaniya Das compatible: 20ced3aaeaSTaniya Das const: qcom,sc7280-dispcc 21ced3aaeaSTaniya Das 22ced3aaeaSTaniya Das clocks: 23ced3aaeaSTaniya Das items: 24ced3aaeaSTaniya Das - description: Board XO source 25ced3aaeaSTaniya Das - description: GPLL0 source from GCC 26ced3aaeaSTaniya Das - description: Byte clock from DSI PHY 27ced3aaeaSTaniya Das - description: Pixel clock from DSI PHY 28ced3aaeaSTaniya Das - description: Link clock from DP PHY 29ced3aaeaSTaniya Das - description: VCO DIV clock from DP PHY 30ced3aaeaSTaniya Das - description: Link clock from EDP PHY 31ced3aaeaSTaniya Das - description: VCO DIV clock from EDP PHY 32ced3aaeaSTaniya Das 33ced3aaeaSTaniya Das clock-names: 34ced3aaeaSTaniya Das items: 35ced3aaeaSTaniya Das - const: bi_tcxo 36ced3aaeaSTaniya Das - const: gcc_disp_gpll0_clk 37ced3aaeaSTaniya Das - const: dsi0_phy_pll_out_byteclk 38ced3aaeaSTaniya Das - const: dsi0_phy_pll_out_dsiclk 39ced3aaeaSTaniya Das - const: dp_phy_pll_link_clk 40ced3aaeaSTaniya Das - const: dp_phy_pll_vco_div_clk 41ced3aaeaSTaniya Das - const: edp_phy_pll_link_clk 42ced3aaeaSTaniya Das - const: edp_phy_pll_vco_div_clk 43ced3aaeaSTaniya Das 44ced3aaeaSTaniya Das '#clock-cells': 45ced3aaeaSTaniya Das const: 1 46ced3aaeaSTaniya Das 47ced3aaeaSTaniya Das '#reset-cells': 48ced3aaeaSTaniya Das const: 1 49ced3aaeaSTaniya Das 50ced3aaeaSTaniya Das '#power-domain-cells': 51ced3aaeaSTaniya Das const: 1 52ced3aaeaSTaniya Das 53ced3aaeaSTaniya Das reg: 54ced3aaeaSTaniya Das maxItems: 1 55ced3aaeaSTaniya Das 56ced3aaeaSTaniya Dasrequired: 57ced3aaeaSTaniya Das - compatible 58ced3aaeaSTaniya Das - reg 59ced3aaeaSTaniya Das - clocks 60ced3aaeaSTaniya Das - clock-names 61ced3aaeaSTaniya Das - '#clock-cells' 62ced3aaeaSTaniya Das - '#reset-cells' 63ced3aaeaSTaniya Das - '#power-domain-cells' 64ced3aaeaSTaniya Das 65ced3aaeaSTaniya DasadditionalProperties: false 66ced3aaeaSTaniya Das 67ced3aaeaSTaniya Dasexamples: 68ced3aaeaSTaniya Das - | 69ced3aaeaSTaniya Das #include <dt-bindings/clock/qcom,gcc-sc7280.h> 70ced3aaeaSTaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 71ced3aaeaSTaniya Das clock-controller@af00000 { 72ced3aaeaSTaniya Das compatible = "qcom,sc7280-dispcc"; 73ced3aaeaSTaniya Das reg = <0x0af00000 0x200000>; 74ced3aaeaSTaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 75ced3aaeaSTaniya Das <&gcc GCC_DISP_GPLL0_CLK_SRC>, 76ced3aaeaSTaniya Das <&dsi_phy 0>, 77ced3aaeaSTaniya Das <&dsi_phy 1>, 78ced3aaeaSTaniya Das <&dp_phy 0>, 79ced3aaeaSTaniya Das <&dp_phy 1>, 80ced3aaeaSTaniya Das <&edp_phy 0>, 81ced3aaeaSTaniya Das <&edp_phy 1>; 82ced3aaeaSTaniya Das clock-names = "bi_tcxo", 83ced3aaeaSTaniya Das "gcc_disp_gpll0_clk", 84ced3aaeaSTaniya Das "dsi0_phy_pll_out_byteclk", 85ced3aaeaSTaniya Das "dsi0_phy_pll_out_dsiclk", 86ced3aaeaSTaniya Das "dp_phy_pll_link_clk", 87ced3aaeaSTaniya Das "dp_phy_pll_vco_div_clk", 88ced3aaeaSTaniya Das "edp_phy_pll_link_clk", 89ced3aaeaSTaniya Das "edp_phy_pll_vco_div_clk"; 90ced3aaeaSTaniya Das #clock-cells = <1>; 91ced3aaeaSTaniya Das #reset-cells = <1>; 92ced3aaeaSTaniya Das #power-domain-cells = <1>; 93ced3aaeaSTaniya Das }; 94ced3aaeaSTaniya Das... 95