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/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drzg2l_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * RZ/G2L MIPI DSI Encoder Driver
45 unsigned int lanes; member
163 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) in rzg2l_mipi_dsi_phy_write() argument
165 iowrite32(data, dsi->mmio + reg); in rzg2l_mipi_dsi_phy_write()
168 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) in rzg2l_mipi_dsi_link_write() argument
170 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_write()
173 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) in rzg2l_mipi_dsi_phy_read() argument
175 return ioread32(dsi->mmio + reg); in rzg2l_mipi_dsi_phy_read()
178 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) in rzg2l_mipi_dsi_link_read() argument
[all …]
H A Drcar_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MIPI DSI Encoder
70 struct clk *dsi; member
75 unsigned int lanes; member
176 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data) in rcar_mipi_dsi_write() argument
178 iowrite32(data, dsi->mmio + reg); in rcar_mipi_dsi_write()
181 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg) in rcar_mipi_dsi_read() argument
183 return ioread32(dsi->mmio + reg); in rcar_mipi_dsi_read()
186 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr) in rcar_mipi_dsi_clr() argument
188 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr); in rcar_mipi_dsi_clr()
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
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/openbmc/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
251 u32 lanes; member
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/openbmc/linux/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen() local
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
32 static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
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/openbmc/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
91 u32 lanes; member
98 struct dw_dsi dsi; member
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
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/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
40 unsigned int lanes; member
71 unsigned int lanes; member
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
15 to four data lanes.
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
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H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
15 up to four data lanes.
18 - $ref: /schemas/display/dsi-controller.yaml#
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H A Dadi,adv7533.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.
20 - adi,adv7533
21 - adi,adv7535
35 reg-names:
38 needing a non-default address.
41 - const: main
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H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
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H A Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
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/openbmc/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
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H A Dti,omap4-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Draydium,rm67191.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
10 - Robert Chiras <robert.chiras@nxp.com>
13 - $ref: panel-common.yaml#
21 reset-gpios: true
22 width-mm: true
23 height-mm: true
25 dsi-lanes:
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/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
202 unsigned int lanes; member
223 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
225 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
227 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
230 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
233 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); in mtk_dsi_phy_timconfig()
234 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
236 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
237 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
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/openbmc/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
25 /* DSI digital registers & bit definitions */
29 /* DSI wrapper registers & bit definitions */
32 #define WCFGR_DSIM BIT(0) /* DSI Mode */
36 #define WCR_DSIEN BIT(3) /* DSI ENable */
44 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
60 /* dsi color format coding according to the datasheet */
80 struct dw_mipi_dsi *dsi; member
87 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
89 writel(val, dsi->base + reg); in dsi_write()
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/openbmc/linux/drivers/gpu/drm/
H A Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
101 * drm_of_component_probe - Generic probe function for a component based master
121 if (!dev->of_node) in drm_of_component_probe()
122 return -EINVAL; in drm_of_component_probe()
129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
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/openbmc/linux/include/drm/
H A Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MIPI DSI Bus
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
24 * struct mipi_dsi_msg - read/write DSI buffer
49 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
67 * struct mipi_dsi_host_ops - DSI bus operations
68 * @attach: attach DSI device to DSI host
69 * @detach: detach DSI device from DSI host
70 * @transfer: transmit a DSI packet
72 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
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/openbmc/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/phy/phy-mipi-dphy.h>
25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
72 #define DATA_LANE_EN(x) BIT((x) - 1)
448 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
450 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
462 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
467 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
472 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
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/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-himax-hx8394.c1 // SPDX-License-Identifier: GPL-2.0
5 * - HannStar HSD060BHW4 5.99" MIPI-DSI panel
9 * Based on drivers/gpu/drm/panel/panel-sitronix-st7703.c
15 #include <linux/media-bus-format.h>
27 #define DRV_NAME "panel-himax-hx8394"
29 /* Manufacturer specific commands sent via DSI, listed in HX8394-F datasheet */
78 unsigned int lanes; member
91 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in hsd060bhw4_init_sequence() local
94 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
98 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
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H A Dpanel-sitronix-st7703.c1 // SPDX-License-Identifier: GPL-2.0
5 * - Rocktech jh057n00900 5.5" MIPI-DSI panel
13 #include <linux/media-bus-format.h>
26 #define DRV_NAME "panel-sitronix-st7703"
28 /* Manufacturer specific Commands send via DSI */
69 unsigned int lanes; member
82 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in jh057n_init_sequence() local
89 mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
91 mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF, in jh057n_init_sequence()
94 mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR, in jh057n_init_sequence()
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/openbmc/linux/include/drm/bridge/
H A Ddw_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 unsigned long mode_flags, u32 lanes, u32 format,
44 struct mipi_dsi_device *dsi);
46 struct mipi_dsi_device *dsi);
56 u32 lanes, u32 format);
67 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi);
68 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder);
69 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi);
70 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave);
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 10nm PHY
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
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