1efdbd734SRob HerringTexas Instruments OMAP5 Display Subsystem 2efdbd734SRob Herring========================================= 3efdbd734SRob Herring 4efdbd734SRob HerringSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 5efdbd734SRob Herringdescription about OMAP Display Subsystem bindings. 6efdbd734SRob Herring 7efdbd734SRob HerringDSS Core 8efdbd734SRob Herring-------- 9efdbd734SRob Herring 10efdbd734SRob HerringRequired properties: 11efdbd734SRob Herring- compatible: "ti,omap5-dss" 12efdbd734SRob Herring- reg: address and length of the register space 13efdbd734SRob Herring- ti,hwmods: "dss_core" 14efdbd734SRob Herring- clocks: handle to fclk 15efdbd734SRob Herring- clock-names: "fck" 16efdbd734SRob Herring 17efdbd734SRob HerringRequired nodes: 18efdbd734SRob Herring- DISPC 19efdbd734SRob Herring 20efdbd734SRob HerringOptional nodes: 21efdbd734SRob Herring- DSS Submodules: RFBI, DSI, HDMI 22efdbd734SRob Herring- Video port for DPI output 23efdbd734SRob Herring 24efdbd734SRob HerringDPI Endpoint required properties: 25efdbd734SRob Herring- data-lines: number of lines used 26efdbd734SRob Herring 27efdbd734SRob Herring 28efdbd734SRob HerringDISPC 29efdbd734SRob Herring----- 30efdbd734SRob Herring 31efdbd734SRob HerringRequired properties: 32efdbd734SRob Herring- compatible: "ti,omap5-dispc" 33efdbd734SRob Herring- reg: address and length of the register space 34efdbd734SRob Herring- ti,hwmods: "dss_dispc" 35efdbd734SRob Herring- interrupts: the DISPC interrupt 36efdbd734SRob Herring- clocks: handle to fclk 37efdbd734SRob Herring- clock-names: "fck" 38efdbd734SRob Herring 39*32fdb624SPeter UjfalusiOptional properties: 40*32fdb624SPeter Ujfalusi- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 41*32fdb624SPeter Ujfalusi in bytes per second 42*32fdb624SPeter Ujfalusi 43efdbd734SRob Herring 44efdbd734SRob HerringRFBI 45efdbd734SRob Herring---- 46efdbd734SRob Herring 47efdbd734SRob HerringRequired properties: 48efdbd734SRob Herring- compatible: "ti,omap5-rfbi" 49efdbd734SRob Herring- reg: address and length of the register space 50efdbd734SRob Herring- ti,hwmods: "dss_rfbi" 51efdbd734SRob Herring- clocks: handles to fclk and iclk 52efdbd734SRob Herring- clock-names: "fck", "ick" 53efdbd734SRob Herring 54efdbd734SRob HerringOptional nodes: 55efdbd734SRob Herring- Video port for RFBI output 56efdbd734SRob Herring- RFBI controlled peripherals 57efdbd734SRob Herring 58efdbd734SRob Herring 59efdbd734SRob HerringDSI 60efdbd734SRob Herring--- 61efdbd734SRob Herring 62efdbd734SRob HerringRequired properties: 63efdbd734SRob Herring- compatible: "ti,omap5-dsi" 64efdbd734SRob Herring- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' 65efdbd734SRob Herring- reg-names: "proto", "phy", "pll" 66efdbd734SRob Herring- interrupts: the DSI interrupt line 67efdbd734SRob Herring- ti,hwmods: "dss_dsi1" or "dss_dsi2" 68efdbd734SRob Herring- vdd-supply: power supply for DSI 69efdbd734SRob Herring- clocks: handles to fclk and pll clock 70efdbd734SRob Herring- clock-names: "fck", "sys_clk" 71efdbd734SRob Herring 72efdbd734SRob HerringOptional nodes: 73efdbd734SRob Herring- Video port for DSI output 74efdbd734SRob Herring- DSI controlled peripherals 75efdbd734SRob Herring 76efdbd734SRob HerringDSI Endpoint required properties: 77efdbd734SRob Herring- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, 78efdbd734SRob Herring DATA1+, DATA1-, ... 79efdbd734SRob Herring 80efdbd734SRob Herring 81efdbd734SRob HerringHDMI 82efdbd734SRob Herring---- 83efdbd734SRob Herring 84efdbd734SRob HerringRequired properties: 85efdbd734SRob Herring- compatible: "ti,omap5-hdmi" 86efdbd734SRob Herring- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 87efdbd734SRob Herring 'core' 88efdbd734SRob Herring- reg-names: "wp", "pll", "phy", "core" 89efdbd734SRob Herring- interrupts: the HDMI interrupt line 90efdbd734SRob Herring- ti,hwmods: "dss_hdmi" 91efdbd734SRob Herring- vdda-supply: vdda power supply 92efdbd734SRob Herring- clocks: handles to fclk and pll clock 93efdbd734SRob Herring- clock-names: "fck", "sys_clk" 94efdbd734SRob Herring 95efdbd734SRob HerringOptional nodes: 96efdbd734SRob Herring- Video port for HDMI output 97efdbd734SRob Herring 98efdbd734SRob HerringHDMI Endpoint optional properties: 99efdbd734SRob Herring- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 100efdbd734SRob Herring D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) 101