| /openbmc/qemu/hw/intc/ |
| H A D | trace-events | 25 ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) "ioapic mem read addr 0x%…
35 slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0…
36 slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" =…
37 slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d…
38 slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq m…
39 slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = 0x%x"
43 slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
45 slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d …
46 slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
51 grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
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| /openbmc/qemu/docs/specs/ |
| H A D | acpi_cpu_hotplug.rst | 1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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| /openbmc/linux/tools/perf/util/ |
| H A D | cpumap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 /** Identify where counts are aggregated, -1 implies not to aggregate. */
14 /** The numa node X as read from /sys/devices/system/node/nodeX. */
17 * The socket number as read from
18 * /sys/devices/system/cpu/cpuX/topology/physical_package_id.
21 /** The die id as read from /sys/devices/system/cpu/cpuX/topology/die_id. */
23 /** The cache level as read from /sys/devices/system/cpu/cpuX/cache/indexY/level */
26 * The cache instance ID, which is the first CPU in the
27 * /sys/devices/system/cpu/cpuX/cache/indexY/shared_cpu_list
30 /** The core id as read from /sys/devices/system/cpu/cpuX/topology/core_id. */
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| /openbmc/linux/tools/virtio/virtio-trace/ |
| H A D | trace-agent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Guest agent for virtio-trace
15 #include "trace-agent.h"
23 #define READ_PATH_FMT "%s/per_cpu/cpu%d/trace_pipe_raw"
24 #define WRITE_PATH_FMT "/dev/virtio-ports/trace-path-cpu%d"
25 #define CTL_PATH "/dev/virtio-ports/agent-ctl-path"
35 pr_err("Could not read cpus\n"); in get_total_cpus()
59 s->pipe_size = PIPE_INIT; in agent_info_new()
60 s->use_stdout = false; in agent_info_new()
61 s->cpus = get_total_cpus(); in agent_info_new()
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| H A D | trace-agent-rw.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Read/write thread of a guest agent for virtio-trace
16 #include "trace-agent.h"
30 rw_ti->cpu_num = -1; in rw_thread_info_new()
31 rw_ti->in_fd = -1; in rw_thread_info_new()
32 rw_ti->out_fd = -1; in rw_thread_info_new()
33 rw_ti->read_pipe = -1; in rw_thread_info_new()
34 rw_ti->write_pipe = -1; in rw_thread_info_new()
35 rw_ti->pipe_size = PIPE_INIT; in rw_thread_info_new()
40 void *rw_thread_init(int cpu, const char *in_path, const char *out_path, in rw_thread_init() argument
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | data-fabric.json | 4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
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| /openbmc/linux/Documentation/core-api/ |
| H A D | local_ops.rst | 29 Local atomic operations are meant to provide fast and highly reentrant per CPU
34 Having fast per CPU atomic counters is interesting in many cases: it does not
40 CPU which owns the data. Therefore, care must taken to make sure that only one
41 CPU writes to the ``local_t`` data. This is done by using per cpu data and
43 however permitted to read ``local_t`` data from any CPU: it will then appear to
44 be written out of order wrt other memory writes by the owner CPU.
54 ``asm-generic/local.h`` in your architecture's ``local.h`` is sufficient.
66 * Variables touched by local ops must be per cpu variables.
67 * *Only* the CPU owner of these variables must write to them.
68 * This CPU can use local ops from any context (process, irq, softirq, nmi, ...)
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| /openbmc/linux/drivers/infiniband/ulp/rtrs/ |
| H A D | rtrs-clt-stats.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-clt.h"
16 struct rtrs_clt_path *clt_path = to_clt_path(con->c.path); in rtrs_clt_update_wc_stats()
17 struct rtrs_clt_stats *stats = clt_path->stats; in rtrs_clt_update_wc_stats()
19 int cpu; in rtrs_clt_update_wc_stats() local
21 cpu = raw_smp_processor_id(); in rtrs_clt_update_wc_stats()
22 s = get_cpu_ptr(stats->pcpu_stats); in rtrs_clt_update_wc_stats()
[all …]
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| H A D | rtrs-srv-stats.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-srv.h"
17 int cpu; in rtrs_srv_reset_rdma_stats() local
20 for_each_possible_cpu(cpu) { in rtrs_srv_reset_rdma_stats()
21 r = per_cpu_ptr(stats->rdma_stats, cpu); in rtrs_srv_reset_rdma_stats()
28 return -EINVAL; in rtrs_srv_reset_rdma_stats()
33 int cpu; in rtrs_srv_stats_rdma_to_str() local
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| /openbmc/linux/drivers/hwtracing/coresight/ |
| H A D | coresight-trace-id.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 * With multi cpu systems, and more additional trace sources a scalable
19 * In order to ensure that a consistent cpu / ID matching is maintained
20 * throughout a perf cs_etm event session - a session in progress flag will
22 * complete. This allows the same CPU to be re-allocated its prior ID.
28 * API permits multiple maps to be maintained - for large systems where
55 * @pend_rel_ids: CPU IDs that have been released by the trace source but not
56 * yet marked as available, to allow re-allocation to the same
57 * CPU during a perf session.
67 * Read and optionally allocate a CoreSight trace ID and associate with a CPU.
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| /openbmc/linux/tools/power/cpupower/utils/helpers/ |
| H A D | sysfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
24 if (fd == -1) in sysfs_read_file()
27 numread = read(fd, buf, buflen - 1); in sysfs_read_file()
40 * Detect whether a CPU is online
43 * 1 -> if CPU is online
44 * 0 -> if CPU is offline
47 int sysfs_is_cpu_online(unsigned int cpu) in sysfs_is_cpu_online() argument
57 snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u", cpu); in sysfs_is_cpu_online()
64 * -> cpuX directory exists, but not cpuX/online file in sysfs_is_cpu_online()
[all …]
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| H A D | msr.c | 1 // SPDX-License-Identifier: GPL-2.0
19 * Will return 0 on success and -1 on failure.
21 * EFAULT -If the read/write did not fully complete
22 * EIO -If the CPU does not support MSRs
23 * ENXIO -If the CPU does not exist
26 int read_msr(int cpu, unsigned int idx, unsigned long long *val) in read_msr() argument
31 sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu); in read_msr()
34 return -1; in read_msr()
35 if (lseek(fd, idx, SEEK_CUR) == -1) in read_msr()
37 if (read(fd, val, sizeof *val) != sizeof *val) in read_msr()
[all …]
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| /openbmc/linux/arch/arm/mach-zynq/ |
| H A D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
49 * @val: Pointer to value to be read from SLCR
60 * zynq_slcr_unlock - Unlock SLCR registers
72 * zynq_slcr_get_device_id - Read device code id
88 * zynq_slcr_system_restart - Restart the entire system.
104 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
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| /openbmc/linux/include/uapi/linux/ |
| H A D | isst_if.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * struct isst_if_platform_info - Define platform information
25 * @mmio_supported: Support of mmio interface for core-power feature
40 * struct isst_if_cpu_map - CPU mapping between logical and physical CPU
41 * @logical_cpu: Linux logical CPU number
42 * @physical_cpu: PUNIT CPU number
44 * Used to convert from Linux logical CPU to PUNIT CPU numbering scheme.
45 * The PUNIT CPU number is different than APIC ID based CPU numbering.
53 * struct isst_if_cpu_maps - structure for CPU map IOCTL
54 * @cmd_count: Number of CPU mapping command in cpu_map[]
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| /openbmc/linux/tools/power/cpupower/lib/ |
| H A D | cpuidle.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
22 * For example the functionality to disable c-states was introduced in later
29 unsigned int cpuidle_state_file_exists(unsigned int cpu, in cpuidle_state_file_exists() argument
37 snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u/cpuidle/state%u/%s", in cpuidle_state_file_exists()
38 cpu, idlestate, fname); in cpuidle_state_file_exists()
45 * helper function to read file from /sys into given buffer
51 unsigned int cpuidle_state_read_file(unsigned int cpu, in cpuidle_state_read_file() argument
60 snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u/cpuidle/state%u/%s", in cpuidle_state_read_file()
61 cpu, idlestate, fname); in cpuidle_state_read_file()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 adr r0, reset /* r0 <- Runtime value of reset */
50 ldr r1, =reset /* r1 <- Linked value of reset */
51 subs r4, r0, r1 /* r4 <- Run-vs-link offset */
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| /openbmc/linux/tools/memory-model/Documentation/ |
| H A D | explanation.txt | 1 Explanation of the Linux-Kernel Memory Consistency Model
15 7. THE PROGRAM ORDER RELATION: po AND po-loc
18 10. THE READS-FROM RELATION: rf, rfi, and rfe
20 12. THE FROM-READS RELATION: fr, fri, and fre
22 14. PROPAGATION ORDER RELATION: cumul-fence
28 20. THE HAPPENS-BEFORE RELATION: hb
29 21. THE PROPAGATES-BEFORE RELATION: pb
30 22. RCU RELATIONS: rcu-link, rcu-gp, rcu-rscsi, rcu-order, rcu-fence, and rb
31 23. SRCU READ-SIDE CRITICAL SECTIONS
39 ------------
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| /openbmc/qemu/hw/ppc/ |
| H A D | pnv_core.c | 2 * QEMU PowerPC PowerNV CPU Core model
25 #include "target/ppc/cpu.h"
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_reset() argument
47 CPUState *cs = CPU(cpu); in pnv_core_cpu_reset()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
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| /openbmc/linux/arch/ia64/kernel/ |
| H A D | salinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (c) 2003 Hewlett-Packard Co
14 * Replace IPI with set_cpus_allowed() to read a record from the required cpu.
17 * Cache the record across multi-block reads from user space.
30 * Replace some NR_CPUS by cpus_online, for hotplug cpu.
36 * Replace the counting semaphore with a mutex and a test if the cpumask is non-empty.
41 #include <linux/cpu.h>
55 MODULE_DESCRIPTION("/proc interface to IA-64 SAL features");
97 int cpu; member
100 /* State transitions. Actions are :-
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| /openbmc/linux/arch/mips/include/asm/sn/sn0/ |
| H A D | hubpi.h | 8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
28 #define PI_CPU_PROTECT 0x000000 /* CPU Protection */
29 #define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
32 #define PI_CPU_NUM 0x000020 /* CPU Number ID */
57 #define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */
58 #define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */
59 #define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */
60 #define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */
63 #define PI_NMI_A 0x000070 /* NMI to CPU A */
64 #define PI_NMI_B 0x000078 /* NMI to CPU B */
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| /openbmc/linux/kernel/trace/ |
| H A D | ring_buffer.c | 1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/cpu.h>
66 * allocated for each CPU. A writer may only write to a buffer that is
67 * associated with the CPU it is currently executing on. A reader may read
68 * from any per cpu buffer.
70 * The reader is special. For each per cpu buffer, the reader has its own
71 * reader page. When a reader has read the entire reader page, this reader
80 * +------+
83 * +------+ +---+ +---+ +---+
84 * | |-->| |-->| |
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| /openbmc/linux/Documentation/ |
| H A D | memory-barriers.txt | 19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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| /openbmc/linux/tools/power/cpupower/utils/idle_monitor/ |
| H A D | mperf_monitor.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include "idle_monitor/cpupower-monitor.h"
33 unsigned int cpu);
35 unsigned int cpu);
80 /* valid flag for all CPUs. If a MSR read failed it will be zero */
93 static int get_aperf_mperf(int cpu, unsigned long long *aval, in get_aperf_mperf() argument
101 * Running on the cpu from which we read the registers will in get_aperf_mperf()
106 if (bind_cpu(cpu)) in get_aperf_mperf()
124 ret = read_msr(cpu, MSR_APERF, aval); in get_aperf_mperf()
125 ret |= read_msr(cpu, MSR_MPERF, mval); in get_aperf_mperf()
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| /openbmc/linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
28 u32 *cpu; in cpu_set() local
31 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
32 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
36 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
38 cpu = map + offset_in_page(offset); in cpu_set()
41 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
43 *cpu = v; in cpu_set()
46 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
49 i915_gem_object_finish_access(ctx->obj); in cpu_set()
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| /openbmc/linux/Documentation/RCU/Design/Requirements/ |
| H A D | Requirements.rst | 16 ------------
18 Read-copy update (RCU) is a synchronization mechanism that is often used
19 as a replacement for reader-writer locking. RCU is unusual in that
20 updaters do not block readers, which means that RCU's read-side
28 thought of as an informal, high-level specification for RCU. It is
40 #. `Fundamental Non-Requirements`_
42 #. `Quality-of-Implementation Requirements`_
44 #. `Software-Engineering Requirements`_
53 ------------------------
58 #. `Grace-Period Guarantee`_
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