Home
last modified time | relevance | path

Searched +full:clk +full:- +full:out +full:- +full:frequency +full:- +full:hz (Results 1 – 25 of 245) sorted by relevance

12345678910

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
57 writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), in twd_set_periodic()
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-evk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 /dts-v1/;
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16 stdout-path = &uart1;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
30 reg_pcie1: regulator-pcie {
[all …]
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
[all …]
H A Dimx8mm-innocomm-wb15.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_regulator>;
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-name = "epdev_on";
18 enable-active-high;
[all …]
H A Dimx8mm-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 model = "Variscite VAR-SOM-MX8MM module";
11 compatible = "variscite,var-som-mx8mm", "fsl,imx8mm";
14 stdout-path = &uart4;
22 reg_eth_phy: regulator-eth-phy {
23 compatible = "regulator-fixed";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
26 regulator-name = "eth_phy_pwr";
27 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mn-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 compatible = "mmc-pwrseq-simple";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
17 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
19 clock-names = "ext_clock";
20 post-power-on-delay-ms = <80>;
30 cpu-supply = <&buck2_reg>;
34 cpu-supply = <&buck2_reg>;
38 cpu-supply = <&buck2_reg>;
[all …]
H A Dimx8mm-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 compatible = "mmc-pwrseq-simple";
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
16 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
18 clock-names = "ext_clock";
19 post-power-on-delay-ms = <80>;
29 cpu-supply = <&buck2_reg>;
33 cpu-supply = <&buck2_reg>;
37 cpu-supply = <&buck2_reg>;
[all …]
H A Dimx8mm-venice-gw7904.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
20 stdout-path = &uart2;
28 gpio-keys {
29 compatible = "gpio-keys";
[all …]
/openbmc/linux/drivers/devfreq/
H A Drk3399_dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
9 #include <linux/clk.h>
12 #include <linux/devfreq-event.h>
44 struct clk *dmc_clk;
74 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
92 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
95 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
44 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
[all …]
H A Dclk_rk3399.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3399-cru.h>
41 ((input_rate) / (output_rate) - 1);
44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
306 * FOUTVCO = Fractional PLL non-divided output frequency
[all …]
H A Dclk_rk3288.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
72 /* CLKSEL1: pd bus clk pll sel: codec or general */
133 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
[all …]
/openbmc/linux/drivers/clocksource/
H A Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
[all …]
/openbmc/u-boot/drivers/spi/
H A Drk_spi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * (C) Copyright 2008-2013 Rockchip Electronics
12 #include <clk.h>
14 #include <dt-structs.h>
31 s32 frequency; /* Default clock frequency, -1 for none */ member
39 struct clk clk; member
55 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
56 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1)); in rkspi_dump_regs()
57 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr)); in rkspi_dump_regs()
58 debug("ser: \t\t0x%08x\n", readl(&regs->ser)); in rkspi_dump_regs()
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328-orangepi-r1-plus-lts.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-orangepi-r1-plus.dts"
14 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
18 /delete-property/ tx_delay;
19 /delete-property/ rx_delay;
21 phy-handle = <&yt8531c>;
22 phy-mode = "rgmii-id";
25 /delete-node/ ethernet-phy@1;
[all …]
H A Drk3328-nanopi-r2c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-nanopi-r2s.dts"
14 compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
18 phy-handle = <&yt8521s>;
23 /delete-node/ ethernet-phy@1;
25 yt8521s: ethernet-phy@3 {
26 compatible = "ethernet-phy-ieee802.3-c22";
29 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
35 struct clk *null_clk;
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
[all …]
/openbmc/u-boot/drivers/sound/
H A Dwm8994.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
31 int in; /* Input frequency in Hz */
32 int out; /* output frequency in Hz */ member
39 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
40 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
41 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
84 return dm_i2c_write(priv->dev, reg, val, 2); in wm8994_i2c_write()
94 * @return int value 0 for success, -1 in case of error.
102 ret = dm_i2c_read(priv->dev, reg, val, 1); in wm8994_i2c_read()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
[all …]
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
12 #include <dt-bindings/clock/ast2400-clock.h>
13 #include <dt-bindings/reset/ast2400-reset.h>
19 * For H-PLL and M-PLL the formula is
20 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
21 * M - Numerator
22 * N - Denumerator
23 * P - Post Divider
26 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-si570.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2011 - 2021 Xilinx Inc.
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
57 * @max_freq: Maximum frequency for this device
58 * @fxtal: Factory xtal frequency
62 * @frequency: Current output frequency
74 u64 frequency; member
85 * si570_get_divs() - Read clock dividers from HW
101 err = regmap_bulk_read(data->regmap, SI570_REG_HS_N1 + data->div_offset, in si570_get_divs()
[all …]
/openbmc/linux/drivers/thermal/st/
H A Dstm_thermal.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
91 struct clk *clk; member
103 dev_dbg(sensor->dev, "low:%d high:%d\n", sensor->low_temp_enabled, in stm_enable_irq()
104 sensor->high_temp_enabled); in stm_enable_irq()
107 value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET); in stm_enable_irq()
110 if (sensor->low_temp_enabled) in stm_enable_irq()
113 if (sensor->high_temp_enabled) in stm_enable_irq()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]

12345678910