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/openbmc/linux/drivers/clk/bcm/
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
51 .reset = RESET_VAL(0x0, 11, 10),
54 .ndiv_int = REG_VAL(0x10, 20, 10),
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
72 .mdiv = REG_VAL(0x20, 10, 8),
[all …]
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
41 .ndiv_int = REG_VAL(0x10, 20, 10),
49 .channel = BCM_SR_GENPLL0_125M_CLK,
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
58 .mdiv = REG_VAL(0x18, 10, 9),
61 .channel = BCM_SR_GENPLL0_250M_CLK,
67 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_at_ao.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
/openbmc/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* MIDI 1.0 Channel Control (7bit) */
37 UMP_CC_PAN = 10,
134 u32 channel:4; member
140 u32 channel:4;
153 u32 channel:4; member
159 u32 channel:4;
172 u32 channel:4; member
178 u32 channel:4;
191 u32 channel:4; member
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DGalaxy19_C-97.0W1 # Galaxy 19 @ 97W C-BAND
3 [CHANNEL]
12 [CHANNEL]
21 [CHANNEL]
26 INNER_FEC = 9/10
30 [CHANNEL]
39 [CHANNEL]
48 [CHANNEL]
57 [CHANNEL]
66 [CHANNEL]
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dda9052.rst6 * Dialog Semiconductors DA9052-BC and DA9053-AA/Bx PMICs
15 -----------
17 The DA9052/53 provides an Analogue to Digital Converter (ADC) with 10 bits
19 multiplexer. The analogue input multiplexer will allow conversion of up to 10
26 Channel 0 VDDOUT - measurement of the system voltage
27 Channel 1 ICH - internal battery charger current measurement
28 Channel 2 TBAT - output from the battery NTC
29 Channel 3 VBAT - measurement of the battery voltage
30 Channel 4 ADC_IN4 - high impedance input (0 - 2.5V)
31 Channel 5 ADC_IN5 - high impedance input (0 - 2.5V)
[all …]
/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
33 /* Channel Image Control Register */
97 #define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10)
98 #define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
143 /* Channel Interrupt Enable Register */
153 /* Channel Status Register */
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dad7476.c1 // SPDX-License-Identifier: GPL-2.0
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
31 struct iio_chan_spec channel[2]; member
80 if (!st->convst_gpio) in ad7091_convst()
83 gpiod_set_value(st->convst_gpio, 0); in ad7091_convst()
84 udelay(1); /* CONVST pulse width: 10 ns min */ in ad7091_convst()
85 gpiod_set_value(st->convst_gpio, 1); in ad7091_convst()
92 struct iio_dev *indio_dev = pf->indio_dev; in ad7476_trigger_handler()
98 b_sent = spi_sync(st->spi, &st->msg); in ad7476_trigger_handler()
102 iio_push_to_buffers_with_timestamp(indio_dev, st->data, in ad7476_trigger_handler()
[all …]
H A Dad799x.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc.
7 * Copyright (C) 2008-2010 Jonathan Cameron
10 * Copyright (C) 2002-2004 Stefan Eletzhofer
101 * struct ad799x_chip_config - chip specific information
102 * @channel: channel specification
107 const struct iio_chan_spec channel[9]; member
113 * struct ad799x_chip_info - chip specific information
140 switch (st->id) { in ad799x_write_config()
143 return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG, in ad799x_write_config()
[all …]
H A Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
73 * struct twl6030_chnl_calib - channel calibration
85 * struct twl6030_ideal_code - GPADC calibration parameters
89 * @channel: channel number
96 int channel; member
106 * struct twl6030_gpadc_platform_data - platform specific data
111 * @channel_to_reg: pointer to ADC function to convert channel to
119 int (*start_conversion)(int channel);
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
32 * bit 10~11 bandwidth
42 #define BRCMU_CHSPEC_D11N_BW_SHIFT 10
52 * bit 8~10 sideband
100 BRCMU_CHAN_SB_NONE = -1,
118 * struct brcmu_chan - stores channel formats
121 * channel info and the other way.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/openbmc/linux/drivers/hwmon/
H A Dpcf8591.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2001-2004 Aurelien Jarno <aurelien@aurel32.net>
52 * Channel selection
53 * 0x00 = channel 0
54 * 0x01 = channel 1
55 * 0x02 = channel 2
56 * 0x03 = channel 3
65 #define REG_TO_SIGNED(reg) (((reg) & 0x80) ? ((reg) - 256) : (reg))
76 static int pcf8591_read_channel(struct device *dev, int channel);
79 #define show_in_channel(channel) \ argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
34 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
35 - ad,ad7414
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
H A Dsprd-mcdt.txt1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
5 supports 10 DAC channel and 10 ADC channel, and each channel can be
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-eeprom-parse.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-modparams.h"
11 #include "iwl-eeprom-parse.h"
75 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
76 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
77 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
78 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
79 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
[all …]
/openbmc/linux/sound/usb/caiaq/
H A Dinput.c1 // SPDX-License-Identifier: GPL-2.0-or-later
105 MASCHINE_BUTTON(10),
125 #define LOW_PEAK (-7)
136 int range = HIGH_PEAK - LOW_PEAK; in decode_erp()
139 weight_b = abs(mid_value - a) - (range / 2 - 100) / 2; in decode_erp()
147 weight_a = 100 - weight_b; in decode_erp()
151 pos_b = b - LOW_PEAK + DEG270; in decode_erp()
153 pos_b -= DEG360; in decode_erp()
156 pos_b = HIGH_PEAK - b + DEG90; in decode_erp()
161 pos_a = a - LOW_PEAK; in decode_erp()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
22 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
23 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
24 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
25 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
49 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
50 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
[all …]
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
51 RF_CHANNEL(10) = 0x57,
[all …]
/openbmc/openbmc/meta-bytedance/meta-g220a/recipes-phosphor/configuration/entity-manager/
H A Dg220a_baseboard.json327 "Index": 10,
589 "Index": 10,
896 10,
947 "Channel": 0, number
963 "Channel": 0, number
979 "Channel": 1, number
995 "Channel": 1, number
1011 "Channel": 0, number
1027 "Channel": 0, number
1043 "Channel": 1, number
[all …]
/openbmc/linux/include/linux/regulator/
H A Dda9121.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
/openbmc/u-boot/drivers/dma/
H A DMCD_tasksInit.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
22 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainNoEu() argument
24 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainNoEu()
40 MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ in MCD_startDmaChainNoEu()
52 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainNoEu()
60 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleNoEu() argument
62 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaSingleNoEu()
77 MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */ in MCD_startDmaSingleNoEu()
83 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleNoEu()
[all …]

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