cache\-time\-ms (full) in projects: openbmc

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/openbmc/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	frontend.json	30 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins… 38 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin… 46 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).… 54 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (… 59 "BriefDescription": "MS decode starts", 62 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
/openbmc/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	frontend.json	30 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins… 38 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin… 46 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).… 54 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (… 59 "BriefDescription": "MS decode starts", 62 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
/openbmc/linux/drivers/md/bcache/
H A D	io.c	1 // SPDX-License-Identifier: GPL-2.0 21 mempool_free(b, &c->bio_meta); in bch_bbio_free() 26 struct bbio b = mempool_alloc(&c->bio_meta, GFP_NOIO); in bch_bbio_alloc() 27 struct bio bio = &b->bio; in bch_bbio_alloc() 29 bio_init(bio, NULL, bio->bi_inline_vecs, in bch_bbio_alloc() 30 meta_bucket_pages(&c->cache->sb), 0); in bch_bbio_alloc() 39 bio->bi_iter.bi_sector = PTR_OFFSET(&b->key, 0); in __bch_submit_bbio() 40 bio_set_dev(bio, c->cache->bdev); in __bch_submit_bbio() 42 b->submit_time_us = local_clock_us(); in __bch_submit_bbio() 43 closure_bio_submit(c, bio, bio->bi_private); in __bch_submit_bbio() [all …]
/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A D	maxim,ds2760.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sebastian Reichel <sre@kernel.org> 13 The ds2760 is a w1 slave device and must hence have its sub-node in 17 - $ref: power-supply.yaml# 23 maxim,pmod-enabled: 29 maxim,cache-time-ms: 31 Time im milliseconds to cache the data for. 32 When this time expires, the values are read again from the hardware. [all …]`
/openbmc/linux/Documentation/core-api/
H A D	workqueue.rst	33 thread system-wide. A single MT wq needed to keep around the same 50 limitation that no two polling PIOs can progress at the same time. As 60 * Use per-CPU unified worker pools shared by all wq to provide 83 called worker-pools. 85 The cmwq design differentiates between the user-facing workqueues that 87 which manages worker-pools and processes the queued work items. 89 There are two worker-pools, one for normal work items and the other 91 worker-pools to serve work items queued on unbound workqueues - the 102 When a work item is queued to a workqueue, the target worker-pool is 104 and appended on the shared worklist of the worker-pool. For example, [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	frontend.json	15 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un… 24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 73 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 85 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 112 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 118 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 124 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 130 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A D	writecache.rst	`6 doesn't cache reads because reads are supposed to be cached in page cache 14 1. type of the cache device - "p" or "s" 15 - p - persistent memory 16 - s - SSD 18 3. the cache device 25 offset from the start of cache device in 512-byte sectors 40 autocommit_time ms (default: 1000) 41 autocommit time in milliseconds. The data is automatically 42 committed if this time passes and no FLUSH request is 45 applicable only to persistent memory - use the FUA flag [all …]`
/openbmc/linux/sound/soc/codecs/
H A D	ssm2518.c	1 // SPDX-License-Identifier: GPL-2.0-only 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 141 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400); 142 static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0); 143 static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0); 144 static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0); 145 static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0); 148 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0), 149 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0), 153 "0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms", [all …]
/openbmc/linux/tools/perf/Documentation/
H A D	perf-trace.txt	`1 perf-trace(1) 5 ---- 6 perf-trace - strace inspired tool 9 -------- 15 ----------- 22 but the session needs to include the raw_syscalls events (-e 'raw_syscalls:*'). 30 ------- 32 -a:: 33 --all-cpus:: 34 System-wide collection from all CPUs. [all …]`
H A D	perf-stat.txt	`1 perf-stat(1) 5 ---- 6 perf-stat - Run a command and gather performance counter statistics 9 -------- 11 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] <command> 12 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] \-- <command> [<options>] 13 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] record [-o file] \-- <command> [<options>] 14 'perf stat' report [-i file] 17 ----------- 23 ------- [all …]`
H A D	tips.txt	1 For a higher level overview, try: perf report --sort comm,dso 2 Sample related events with: perf record -e '{cycles,instructions}:S' 4 Boolean options have negative forms, e.g.: perf report --no-children 5 Customize output of perf script with: perf script -F event,ip,sym 6 Generate a script for your data: perf script -g <lang> 9 Search options using a keyword: perf report -h <keyword> 10 Use parent filter to see specific call path: perf report -p <regex> 12 To see list of saved events and attributes: perf evlist -v 13 Use --symfs <dir> if your symbol files are in non-standard locations 14 To see callchains in a more compact form: perf report -g folded [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", [all …]
/openbmc/qemu/hw/misc/
H A D	mac_via.c	`4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 9 * Copyright (c) 2004-2007 Fabrice Bellard 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 15 * See the COPYING file in the top-level directory. 19 #include "exec/address-spaces.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 77 * state-control line SEL" on all but IIfx [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	frontend.json	15 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un… 24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 53 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 65 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 83 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 89 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 95 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 101 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/qemu/qapi/
H A D	migration.json	1 # -- Mode: Python -- 28 # @normal-bytes: number of normal bytes sent (since 1.2) 30 # @dirty-pages-rate: number of pages dirtied by second by the guest 35 # @dirty-sync-count: number of times that dirty ram was synchronized 38 # @postcopy-requests: The number of page requests received from the 41 # @page-size: The number of bytes per page for the various page-based 44 # @multifd-bytes: The number of bytes sent through multifd (since 3.0) 46 # @pages-per-second: the number of memory pages transferred per second 49 # @precopy-bytes: The number of bytes sent in the pre-copy phase 52 # @downtime-bytes: The number of bytes sent while the guest is paused [all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-dbs/influxdb/influxdb/
H A D	influxdb.conf	`12 # reporting-disabled = false 15 # bind-address = "127.0.0.1:8088" 29 # retention-autocreate = true 32 # logging-enabled = true 48 wal-dir = "/var/lib/influxdb/wal" 50 # The amount of time that a write will wait before fsyncing. A duration 53 # Values in the range of 0-100ms are recommended for non-SSD disks. 54 # wal-fsync-delay = "0s" 57 # The type of shard index to use for new shards. The default is an in-memory index that is 60 # index-version = "inmem" [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	frontend.json	6 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 29 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 40 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 51 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 67 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 73 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 84 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/qemu/migration/
H A D	migration-hmp-cmds.c	10 * the COPYING file in the top-level directory. 12 * Contributions after 2012-01-13 are licensed under the terms of the 22 #include "qapi/qapi-commands-migration.h" 23 #include "qapi/qapi-visit-migration.h" 25 #include "qapi/string-input-visitor.h" 26 #include "qapi/string-output-visitor.h" 28 #include "qemu/error-report.h" 31 #include "ui/qemu-spice.h" 38 MigrationState *ms = migrate_get_current(); in migration_global_dump() local 41 monitor_printf(mon, "store-global-state: %s\n", in migration_global_dump() [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	pipeline.json	160 …time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th… 181 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last … 206 …"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for an… 213 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the allo… 221 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is e… 229 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATsta… 236 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB … 273 …"BriefDescription": "Counts the number of occurrences a retired load that is a cache line split. E… 289 …"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue becaus… 296 …"BriefDescription": "Counts the number of occurrences a retired store that is a cache line split. … [all …]

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