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/openbmc/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra234-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Driscv.c1 // SPDX-License-Identifier: GPL-2.0-only
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors() local
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
51 READ_PROP("nvidia,bl-manifest-offset", &bl->manifest_offset); in tegra_drm_riscv_read_descriptors()
52 READ_PROP("nvidia,bl-code-offset", &bl->code_offset); in tegra_drm_riscv_read_descriptors()
53 READ_PROP("nvidia,bl-data-offset", &bl->data_offset); in tegra_drm_riscv_read_descriptors()
[all …]
/openbmc/linux/fs/nfs/blocklayout/
H A Dblocklayout.c54 switch (be->be_state) { in is_hole()
58 return be->be_tag ? false : true; in is_hole()
64 /* The data we are handed might be spread across several bios. We need
69 void (*pnfs_callback) (void *data);
70 void *data; member
73 static inline struct parallel_io *alloc_parallel(void *data) in alloc_parallel() argument
79 rv->data = data; in alloc_parallel()
80 kref_init(&rv->refcnt); in alloc_parallel()
87 kref_get(&p->refcnt); in get_parallel()
95 p->pnfs_callback(p->data); in destroy_parallel()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
H A Dtu102.c46 u32 offset = 0; in tu102_acr_wpr_build() local
49 /*XXX: shared sub-WPR headers, fill terminator for now. */ in tu102_acr_wpr_build()
50 nvkm_wo32(acr->wpr, 0x200, 0xffffffff); in tu102_acr_wpr_build()
52 /* Fill per-LSF structures. */ in tu102_acr_wpr_build()
53 list_for_each_entry(lsfw, &acr->lsfw, head) { in tu102_acr_wpr_build()
54 struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; in tu102_acr_wpr_build()
56 .falcon_id = lsfw->id, in tu102_acr_wpr_build()
57 .lsb_offset = lsfw->offset.lsb, in tu102_acr_wpr_build()
60 .bin_version = sig->version, in tu102_acr_wpr_build()
65 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); in tu102_acr_wpr_build()
[all …]
H A Dgm200.c42 nvkm_warn(&acr->subdev, "firmware unavailable\n"); in gm200_acr_nofw()
55 struct nvkm_device *device = acr->subdev.device; in gm200_acr_wpr_check()
67 struct nvkm_subdev *subdev = &acr->subdev; in gm200_acr_wpr_patch()
71 u32 offset = 0; in gm200_acr_wpr_patch() local
74 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); in gm200_acr_wpr_patch()
77 list_for_each_entry(lsfw, &acr->lsfw, head) { in gm200_acr_wpr_patch()
78 if (lsfw->id != hdr.falcon_id) in gm200_acr_wpr_patch()
81 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); in gm200_acr_wpr_patch()
84 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); in gm200_acr_wpr_patch()
87 offset += sizeof(hdr); in gm200_acr_wpr_patch()
[all …]
H A Dgp102.c38 u32 offset = 0; in gp102_acr_wpr_patch() local
41 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); in gp102_acr_wpr_patch()
42 wpr_header_v1_dump(&acr->subdev, &hdr); in gp102_acr_wpr_patch()
44 list_for_each_entry(lsfw, &acr->lsfw, head) { in gp102_acr_wpr_patch()
45 if (lsfw->id != hdr.falcon_id) in gp102_acr_wpr_patch()
48 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); in gp102_acr_wpr_patch()
49 lsb_header_v1_dump(&acr->subdev, &lsb); in gp102_acr_wpr_patch()
51 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); in gp102_acr_wpr_patch()
55 offset += sizeof(hdr); in gp102_acr_wpr_patch()
66 if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature))) in gp102_acr_wpr_build_lsb()
[all …]
/openbmc/linux/include/linux/
H A Dbio.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define bio_prio(bio) (bio)->bi_ioprio
23 #define bio_set_prio(bio, prio) ((bio)->bi_ioprio = prio)
26 bvec_iter_bvec((bio)->bi_io_vec, (iter))
29 bvec_iter_page((bio)->bi_io_vec, (iter))
31 bvec_iter_len((bio)->bi_io_vec, (iter))
33 bvec_iter_offset((bio)->bi_io_vec, (iter))
35 #define bio_page(bio) bio_iter_page((bio), (bio)->bi_iter)
36 #define bio_offset(bio) bio_iter_offset((bio), (bio)->bi_iter)
37 #define bio_iovec(bio) bio_iter_iovec((bio), (bio)->bi_iter)
[all …]
/openbmc/qemu/block/
H A Dio.c27 #include "sysemu/block-backend.h"
28 #include "block/aio-wait.h"
33 #include "block/dirty-bitmap.h"
34 #include "block/write-threshold.h"
38 #include "qemu/error-report.h"
39 #include "qemu/main-loop.h"
42 /* Maximum bounce buffer for copy-on-read and write zeroes, in bytes */
49 int64_t offset, int64_t bytes, BdrvRequestFlags flags);
58 QLIST_FOREACH_SAFE(c, &bs->parents, next_parent, next) { in bdrv_parent_drained_begin()
70 assert(c->quiesced_parent); in bdrv_parent_drained_end_single()
[all …]
H A Discsi.c4 * Copyright (c) 2010-2011 Ronnie Sahlberg <ronniesahlberg@gmail.com>
5 * Copyright (c) 2012-2017 Peter Lieven <pl@kamp.de>
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
36 #include "block/block-io.h"
46 #include "qapi/qapi-commands-machine.h"
57 #include <iscsi/scsi-lowlevel.h>
78 struct scsi_inquiry_block_limits bl; member
83 * unallocated pages (iscsilun->lprz) we can directly return zeros instead
143 /* this threshold is a trade-off knob to choose between
[all …]
H A Dfile-posix.c28 #include "qemu/error-report.h"
29 #include "block/block-io.h"
36 #include "block/thread-pool.h"
38 #include "block/raw-aio.h"
42 #include "scsi/pr-manager.h"
149 * s->fd. */
187 BDRVRawState *s = bs->opaque; in fd_open()
189 /* this is just to ensure s->fd is sane (its called by io ops) */ in fd_open()
190 if (s->fd >= 0) { in fd_open()
193 return -EIO; in fd_open()
[all …]
H A Dnvme.c4 * Copyright 2016 - 2018 Red Hat, Inc.
11 * See the COPYING file in the top-level directory.
19 #include "qemu/defer-call.h"
20 #include "qemu/error-report.h"
21 #include "qemu/main-loop.h"
26 #include "qemu/vfio-helpers.h"
27 #include "block/block-io.h"
29 #include "sysemu/block-backend.h"
44 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1)
72 int free_req_next; /* q->reqs[] index of next free req */
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dcrt0_64.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * crt0 - C-runtime startup Code for AArch64 U-Boot
13 #include <asm-offsets.h>
18 * This file handles the target-independent stages of the U-Boot
19 * start-up where a C runtime environment is needed. Its entry point
26 * the GD ('global data') structure, both located in some readily
28 * global data, initialized or not (BSS), are UNAVAILABLE; only
29 * CONSTANT initialized data are available. GD should be zeroed
35 * store any data which must be passed on to later stages. These
36 * data include the relocation destination, the future stack, and
[all …]
/openbmc/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
230 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
242 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
255 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
277 * - Clock recovery vs. channel equalization
278 * - DPRX vs. LTTPR
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
21 /* Get GIC offset
63 bl get_gic_offset
64 bl gic_kick_secondary_cpus
88 /* Set Wuo bit for RN-I 20 */
92 bl ccn504_set_aux
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Datmel_lcdfb.c13 #include <linux/dma-mapping.h>
38 /* LCD Controller info data structure, stored in device platform_data */
69 #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
70 #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
107 /* some bl->props field just changed */
108 static int atmel_bl_update_status(struct backlight_device *bl) in atmel_bl_update_status() argument
110 struct atmel_lcdfb_info *sinfo = bl_get_data(bl); in atmel_bl_update_status()
111 int brightness = backlight_get_brightness(bl); in atmel_bl_update_status()
123 static int atmel_bl_get_brightness(struct backlight_device *bl) in atmel_bl_get_brightness() argument
125 struct atmel_lcdfb_info *sinfo = bl_get_data(bl); in atmel_bl_get_brightness()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
16 #include <asm-offsets.h>
26 #include <asm/u-boot.h>
33 * Set up GOT: Global Offset Table
52 * r3 - 1st arg to board_init(): IMMP pointer
53 * r4 - 2nd arg to board_init(): boot flag
56 .long 0x27051956 /* U-Boot Magic Number */
74 /* Data Storage exception. */
151 bl invalidate_bats
[all …]
H A Dcache.S35 /* use invalidate-all bit in HID0 */
43 * Invalidate L1 data cache.
53 * Flush data cache.
68 * Write any modified data cache blocks out to memory
70 * This is a no-op on the 601.
75 li r5,CACHE_LINE_SIZE-1
95 * Write any modified data cache blocks out to memory.
102 li r5,CACHE_LINE_SIZE-1
104 subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
105 add r4,r4,r5 /* r4 += cache_line_size-1 */
[all …]
/openbmc/qemu/hw/block/
H A Dvirtio-blk.c10 * the COPYING file in the top-level directory.
15 #include "qemu/defer-call.h"
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
24 #include "hw/qdev-properties.h"
26 #include "sysemu/block-ram-registrar.h"
29 #include "hw/virtio/virtio-blk.h"
34 #include "hw/virtio/virtio-bus.h"
35 #include "migration/qemu-file-types.h"
36 #include "hw/virtio/virtio-access.h"
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 #include <asm-offsets.h>
22 #include <asm/boot0-linux-kernel-header.h>
25 * Various SoCs need something special and SoC-specific up front in
45 .quad _end - _start
49 .quad __bss_start - _start
53 .quad __bss_end - _start
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
67 adr x0, _start /* x0 <- Runtime value of _start */
68 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dhead_85xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2004 MontaVista Software, Inc.
40 #include <asm/asm-offsets.h>
43 #include <asm/feature-fixups.h>
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
[all …]
H A Dhead_8xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Low-level exception handlers and MMU support
13 * This file contains low-level support and setup for PowerPC 8xx
30 #include <asm/asm-offsets.h>
32 #include <asm/code-patching-asm.h>
62 * support an ELF compressed (zImage) boot from EPPC-Bug because the
64 * r3: ptr to board info data
66 * r5: initrd_end - unused if r4 is 0
77 * entry into each of the instruction and data TLBs to map the first
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dhead-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
71 * r0 = cp#15 control register (exc_ret for M-class)
90 bl __inflate_kernel_data @ decompress .data to RAM
98 bl __memcpy @ copy .data to RAM
106 bl __memset @ clear .bss
118 bl kasan_early_init
149 .size __mmap_switched_data, . - __mmap_switched_data
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
8 /* U-Boot - Startup Code for PowerPC based Embedded Boards
23 #include <asm-offsets.h>
33 #include <asm/u-boot.h>
41 * Set up GOT: Global Offset Table
60 * r3 - 1st arg to board_init(): IMMP pointer
61 * r4 - 2nd arg to board_init(): boot flag
64 .long 0x27051956 /* U-Boot Magic Number */
76 /*----------------------------------------------------------------------*/
84 /*----------------------------------------------------------------------*/
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmrc_util.c1 // SPDX-License-Identifier: Intel
31 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask) in mrc_write_mask() argument
35 ((data) & (mask))); in mrc_write_mask()
38 void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask) in mrc_alt_write_mask() argument
42 ((data) & (mask))); in mrc_alt_write_mask()
58 /* 1000 MHz clock has 1ns period --> no conversion required */ in delay_n()
70 /* 64-bit math is not an option, just use loops */ in delay_u()
71 while (ms--) in delay_u()
105 * data should be formated using DCMD_Xxxx macro or emrsXCommand structure
107 void dram_init_command(uint32_t data) in dram_init_command() argument
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
13 #include <asm-offsets.h>
25 #include <asm/u-boot.h>
51 * Set up GOT: Global Offset Table
86 * Magic number and version string - put it after the HRCW since it
89 .long 0x27051956 /* U-Boot Magic Number */
139 * vector at offset 0x100 relative to the base set by MSR[IP]. If
170 bl 1f
187 /*------------------------------------------*/
[all …]

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