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/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h44 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b…
49 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB …
51 …{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0…
52 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
55 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling unti…
56 …_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
61 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR …
72 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
77 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b…
88 … PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO sus…
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
371 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
389 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/openbmc/linux/Documentation/input/devices/
H A Dsentelic.rst39 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
42 Byte 4: Bit3~Bit0 => the scrolling wheel's movement since the last data report.
71 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
74 Byte 4: Bit0 => the Vertical scrolling movement downward.
116 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
119 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
140 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
147 Byte 4: Bit7~Bit0 => Don't Care
171 Bit0 => 1
174 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
/openbmc/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
52 byte 255: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp5 ... rp15
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
65 so the sum of all bit0, bit2, bit4 and bit6 values + cp0 itself is even.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c158 * cu_mask[0] bit0 -> se_mask[0] bit0 in mqd_symmetrically_map_cu_mask()
159 * cu_mask[0] bit1 -> se_mask[1] bit0 in mqd_symmetrically_map_cu_mask()
165 * cu_mask[0] bit0 -> se_mask[0] bit0 (SE0,SH0,CU0) in mqd_symmetrically_map_cu_mask()
166 * cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0) in mqd_symmetrically_map_cu_mask()
177 * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0) in mqd_symmetrically_map_cu_mask()
178 * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) in mqd_symmetrically_map_cu_mask()
180 * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0) in mqd_symmetrically_map_cu_mask()
181 * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0) in mqd_symmetrically_map_cu_mask()
/openbmc/linux/drivers/video/fbdev/
H A Dwm8505fb_regs.h16 * BIT0 GOVRH_DVO_YUV2RGB_ENABLE
25 * BIT0 GOVRH_DVO_RGB
49 * BIT0 GOVRH_DVO_OUTWIDTH
/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h10 uint8_t bit0 : 1; member
37 uint8_t bit0 : 1; member
59 uint8_t bit0 : 1; member
97 uint8_t bit0 : 1; member
/openbmc/u-boot/drivers/pch/
H A Dpch9.c33 * Note we don't need check bit0 here, because the Tunnel Creek in pch9_get_gpio_base()
34 * GPIO base address register bit0 is reserved (read returns 0), in pch9_get_gpio_base()
35 * while on the Ivybridge the bit0 is used to indicate it is an in pch9_get_gpio_base()
H A Dpch7.c49 * Note we don't need check bit0 here, because the Tunnel Creek in pch7_get_gpio_base()
50 * GPIO base address register bit0 is reserved (read returns 0), in pch7_get_gpio_base()
51 * while on the Ivybridge the bit0 is used to indicate it is an in pch7_get_gpio_base()
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h73 #define RCR_AAP BIT0
98 #define SCR_TxUseDK BIT0
122 #define IMR_ROK BIT0
181 #define RRSR_1M BIT0
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
145 #bit0=1, enable DDR init upon this register write
/openbmc/libcper/include/libcper/
H A DCper.h43 #define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0
52 #define EFI_ERROR_TIME_STAMP_PRECISE BIT0
178 #define EFI_ERROR_SECTION_FRU_ID_VALID BIT0
185 #define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0
287 #define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0
344 #define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0
411 #define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID BIT0
428 #define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0
481 #define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0
532 #define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86_emu.c933 uint32_t bit0, bit7; in exec_rol() local
938 bit0 = ((uint8_t)decode->op[0].val & 1); in exec_rol()
940 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
951 bit0 = (res & 1); in exec_rol()
953 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
959 uint32_t bit0, bit15; in exec_rol() local
964 bit0 = ((uint16_t)decode->op[0].val & 0x1); in exec_rol()
967 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
975 bit0 = (res & 0x1); in exec_rol()
978 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg85 # bit0: 0, OPEn=OpenPage enabled
103 # bit0: 0, DRAM DLL enabled
143 # bit0: 1, Window enabled
151 # bit0: 1, Window enabled
186 # bit0: 1, enable DDR init upon this register write
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-is2.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 1, Window enabled
144 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/tools/
H A Dvybridimage.c42 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc() local
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
150 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 0x1, Window enabled
146 # bit0: 0x1, enable DDR init upon this register write
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 1, Window enabled
142 #bit0=1, enable DDR init upon this register write

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