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/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dinstruction.json66 …"PublicDescription": "This event counts architecturally executed zero blocking operations due to t…
69 …"BriefDescription": "This event counts architecturally executed zero blocking operations due to th…
72 … "PublicDescription": "This event counts architecturally executed floating-point move operations.",
75 "BriefDescription": "This event counts architecturally executed floating-point move operations."
78 …"PublicDescription": "This event counts architecturally executed operations that using predicate r…
81 …"BriefDescription": "This event counts architecturally executed operations that using predicate re…
84 …"PublicDescription": "This event counts architecturally executed inter-element manipulation operat…
87 …"BriefDescription": "This event counts architecturally executed inter-element manipulation operati…
90 …"PublicDescription": "This event counts architecturally executed inter-register manipulation opera…
93 …"BriefDescription": "This event counts architecturally executed inter-register manipulation operat…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json3 …"PublicDescription": "Instruction architecturally executed, Condition code check pass, software in…
6 …"BriefDescription": "Instruction architecturally executed, Condition code check pass, software inc…
39 … "PublicDescription": "Instruction architecturally executed, condition code check pass, load",
42 "BriefDescription": "Instruction architecturally executed, condition code check pass, load"
45 … "PublicDescription": "Instruction architecturally executed, condition code check pass, store",
48 "BriefDescription": "Instruction architecturally executed, condition code check pass, store"
51 "PublicDescription": "Instruction architecturally executed",
54 "BriefDescription": "Instruction architecturally executed"
63 …"PublicDescription": "Instruction architecturally executed, condition check pass, exception return…
66 … "BriefDescription": "Instruction architecturally executed, condition check pass, exception return"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dretired.json8 "PublicDescription": "Counts instructions that have been architecturally executed."
12 …"PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR register, which usu…
20 …"PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not…
28 …"PublicDescription": "Counts micro-operations that are architecturally executed. This is a count o…
H A Dexception.json4 …"PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError…
8 …"PublicDescription": "Counts any architecturally executed exception return instructions. Eg: AArch…
H A Dmemory.json8 … memory error (from either a speculative and abandoned access, or an architecturally executed acce…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dretired.json8 "PublicDescription": "Counts instructions that have been architecturally executed."
12 …"PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR register, which usu…
20 …"PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not…
H A Dexception.json4 …"PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError…
8 …"PublicDescription": "Counts any architecturally executed exception return instructions. Eg: AArch…
H A Dmemory.json8 … memory error (from either a speculative and abandoned access, or an architecturally executed acce…
/openbmc/linux/drivers/soc/qcom/
H A Dkryo-l2-accessors.c21 * Use architecturally required barriers for ordering between system register
41 * Use architecturally required barriers for ordering between system register
/openbmc/linux/arch/x86/kvm/
H A Dpmu.h47 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is in kvm_pmu_has_perf_global_ctrl()
182 * architecturally required GP counters aren't present, i.e. if in kvm_init_pmu_capability()
184 * is architecturally required. in kvm_init_pmu_capability()
/openbmc/linux/Documentation/arch/arm64/
H A Damu.rst27 of four fixed and architecturally defined 64-bit event counters.
32 - Instructions retired: increments with every architecturally executed
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-trace-id.h25 * Trace ID maps will be created and initialised to prevent architecturally
36 /* architecturally we have 128 IDs some of which are reserved */
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dinstruction.json42 "PublicDescription": "Instruction architecturally executed, software increment",
/openbmc/linux/arch/arm/include/asm/
H A Dvirt.h14 * architecturally defined flag bit here.
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S11 @ RVBAR system register, which is architecturally read-only.
/openbmc/linux/tools/arch/ia64/include/asm/
H A Dbarrier.h22 * architecturally visible effects of a memory access have occurred
/openbmc/linux/arch/x86/include/asm/
H A Dspec-ctrl.h12 * would be easier if SPEC_CTRL were architecturally maskable or
H A Ddebugreg.h125 dr7 &= ~0x400; /* architecturally set bit */ in local_db_save()
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt13 timer interrupt comes from an architecturally mandated real-time timer that is
/openbmc/linux/arch/ia64/include/asm/
H A Dbarrier.h20 * architecturally visible effects of a memory access have occurred
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml36 architecturally connected CTI an additional compatible string is used to
237 # v8 architecturally defined CTI - CPU + ETM connections generated by the
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml51 registers, which contain their architecturally-defined reset values. Only
H A Darm,arch_timer.yaml94 registers, which contain their architecturally-defined reset values. Only
/openbmc/linux/tools/testing/selftests/kvm/x86_64/
H A Dxcr0_cpuid_test.c33 * Assert that KVM reports a sane, usable as-is XCR0. Architecturally, a CPU
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra30-mc.yaml15 Tegra30 Memory Controller architecturally consists of the following parts:

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