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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb3phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
32 XHCI controller#0 -- usb2phy -- phy#0
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H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
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/openbmc/linux/sound/synth/emux/
H A Demux_synth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 1999-2000 Takashi Iwai <tiwai@suse.de>
21 * macro evaluates its args more than once, so changed to upper-case.
59 emu = port->emu; in snd_emux_note_on()
60 if (snd_BUG_ON(!emu || !emu->ops.get_voice || !emu->ops.trigger)) in snd_emux_note_on()
71 if (zp && zp->v.exclusiveClass) in snd_emux_note_on()
72 exclusive_note_off(emu, port, zp->v.exclusiveClass); in snd_emux_note_on()
80 spin_lock_irqsave(&emu->voice_lock, flags); in snd_emux_note_on()
89 vp = emu->ops.get_voice(emu, port); in snd_emux_note_on()
90 if (vp == NULL || vp->ch < 0) in snd_emux_note_on()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
102 * U-Boot to mainline version. in comphy_pcie_power_up()
104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
126 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
135 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_pcie_power_up()
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