Searched +full:amplitude +full:- +full:control +full:- +full:coarse +full:- +full:tuning (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Stanley Chang <stanley_chang@realtek.com>23 XHCI controller#0 -- usb2phy -- phy#024 |- usb3phy -- phy#025 XHCI controller#1 -- usb2phy -- phy#026 XHCI controller#2 -- usb2phy -- phy#027 |- usb3phy -- phy#032 XHCI controller#0 -- usb2phy -- phy#0[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later6 * Copyright (c) 1999-2000 Takashi Iwai <tiwai@suse.de>21 * macro evaluates its args more than once, so changed to upper-case.59 emu = port->emu; in snd_emux_note_on()60 if (snd_BUG_ON(!emu || !emu->ops.get_voice || !emu->ops.trigger)) in snd_emux_note_on()71 if (zp && zp->v.exclusiveClass) in snd_emux_note_on()72 exclusive_note_off(emu, port, zp->v.exclusiveClass); in snd_emux_note_on()80 spin_lock_irqsave(&emu->voice_lock, flags); in snd_emux_note_on()89 vp = emu->ops.get_voice(emu, port); in snd_emux_note_on()90 if (vp == NULL || vp->ch < 0) in snd_emux_note_on()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2015-2016 Marvell International Ltd.31 * For CP-110 we have 2 Selector registers "PHY Selectors",78 } while (data != val && --usec_timout > 0); in polling_with_timeout()100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()102 * U-Boot to mainline version. in comphy_pcie_power_up()104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()126 * we need to configure the clock-source MUX. in comphy_pcie_power_up()135 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_pcie_power_up()[all …]