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/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json520 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
524 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
529 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
533 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
537 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
541 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
546 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
550 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
555 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
559 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json487 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
491 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
496 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
500 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
504 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
508 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
513 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
517 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
522 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
526 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json513 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
517 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
522 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
526 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
530 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
534 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
539 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
543 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
548 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
552 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
[all …]
/openbmc/qemu/tests/qtest/
H A Dtpm-tis-util.c36 DPRINTF("%s: %d: locty=%d l=%d access=0x%02x pending_request_flag=0x%x\n", \
37 __func__, __LINE__, locty, l, access, pending_request_flag)
48 uint8_t access; in tpm_tis_test_check_localities() local
55 access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_localities()
56 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS | in tpm_tis_test_check_localities()
78 uint8_t access; in tpm_tis_test_check_access_reg() local
82 access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_access_reg()
83 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS | in tpm_tis_test_check_access_reg()
89 access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_access_reg()
90 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS | in tpm_tis_test_check_access_reg()
[all …]
H A Dtpm-tis-i2c-test.c33 DPRINTF("%s: %d: locty=%d l=%d access=0x%02x pending_request_flag=0x%x\n", \
34 __func__, __LINE__, locty, l, access, pending_request_flag)
94 uint8_t access; in tpm_tis_i2c_test_basic() local
99 * active locality. Therefore, ensure access is released. in tpm_tis_i2c_test_basic()
103 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_basic()
104 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS | in tpm_tis_i2c_test_basic()
150 /* release access */ in tpm_tis_i2c_test_basic()
163 uint8_t access; in tpm_tis_i2c_test_check_localities() local
169 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_check_localities()
170 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS | in tpm_tis_i2c_test_check_localities()
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/openbmc/linux/Documentation/admin-guide/LSM/
H A DSmack.rst9 Smack is the Simplified Mandatory Access Control Kernel.
10 Smack is a kernel based implementation of mandatory access
13 Smack is not the only Mandatory Access Control scheme
14 available for Linux. Those new to Mandatory Access Control
33 access to systems that use them as Smack does.
50 load the Smack access rules
53 report if a process with one label has access
85 Used to make access control decisions. In almost all cases
95 label does not allow all of the access permitted to a process
102 the Smack rule (more below) that permitted the write access
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/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json7 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
45 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
87 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
104 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
121 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
535 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
543 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
550 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
558 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
566 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
[all …]
/openbmc/skeleton/libopenbmc_intf/
H A Dopenbmc_intf.xml3 <property name="poll_interval" type="i" access="read"/>
4 <property name="sysfs_path" type="s" access="read"/>
5 <property name="scale" type="i" access="read"/>
17 <property name="speed" type="i" access="readwrite"/>
18 <property name="cooling_zone" type="i" access="readwrite"/>
19 <property name="pwm_num" type="i" access="readwrite"/>
34 <property name="value" type="v" access="read"/>
35 <property name="units" type="s" access="read"/>
36 <property name="poll_interval" type="i" access="readwrite"/>
37 <property name="heatbeat" type="i" access="read"/>
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Drecommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
72 "BriefDescription": "L1D tlb access, read"
75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
78 "BriefDescription": "L1D tlb access, write"
81 "PublicDescription": "Attributable Level 2 data cache access, read",
84 "BriefDescription": "L2D cache access, read"
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/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json7 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
45 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
87 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
104 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
121 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
845 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
853 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
860 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
868 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
876 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
[all …]
/openbmc/linux/drivers/iommu/iommufd/
H A Ddevice.c687 * a valid cur_ioas (access->ioas). A caller passing in a valid new_ioas should
690 static int iommufd_access_change_ioas(struct iommufd_access *access, in iommufd_access_change_ioas() argument
693 u32 iopt_access_list_id = access->iopt_access_list_id; in iommufd_access_change_ioas()
694 struct iommufd_ioas *cur_ioas = access->ioas; in iommufd_access_change_ioas()
697 lockdep_assert_held(&access->ioas_lock); in iommufd_access_change_ioas()
700 if (cur_ioas != access->ioas_unpin) in iommufd_access_change_ioas()
708 * iommufd_access_unpin_pages() can continue using access->ioas_unpin. in iommufd_access_change_ioas()
710 access->ioas = NULL; in iommufd_access_change_ioas()
713 rc = iopt_add_access(&new_ioas->iopt, access); in iommufd_access_change_ioas()
715 access->ioas = cur_ioas; in iommufd_access_change_ioas()
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/openbmc/qemu/gdb-xml/
H A Ds390-acr.xml10 <reg name="acr0" bitsize="32" type="uint32" group="access"/>
11 <reg name="acr1" bitsize="32" type="uint32" group="access"/>
12 <reg name="acr2" bitsize="32" type="uint32" group="access"/>
13 <reg name="acr3" bitsize="32" type="uint32" group="access"/>
14 <reg name="acr4" bitsize="32" type="uint32" group="access"/>
15 <reg name="acr5" bitsize="32" type="uint32" group="access"/>
16 <reg name="acr6" bitsize="32" type="uint32" group="access"/>
17 <reg name="acr7" bitsize="32" type="uint32" group="access"/>
18 <reg name="acr8" bitsize="32" type="uint32" group="access"/>
19 <reg name="acr9" bitsize="32" type="uint32" group="access"/>
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h45 * Access: RW
68 * Access: RW
89 * Access: RW
96 * Access: RW
106 * Access: Index
130 * Access: Index
139 * Access: RW
152 * The following register defines the access to the filtering database.
154 * The access is optimized for bulk updates in which case more than one
168 * Access: Index
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/openbmc/linux/include/linux/
H A Dinstrumented.h4 * This header provides generic wrappers for memory access instrumentation that
17 * instrument_read - instrument regular read access
18 * @v: address of access
19 * @size: size of access
21 * Instrument a regular read access. The instrumentation should be inserted
31 * instrument_write - instrument regular write access
32 * @v: address of access
33 * @size: size of access
35 * Instrument a regular write access. The instrumentation should be inserted
45 * instrument_read_write - instrument regular read-write access
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H A Dkcsan-checks.h3 * KCSAN access checks and modifiers. These can be used to explicitly check
16 /* Access types -- if KCSAN_ACCESS_WRITE is not set, the access is a read. */
17 #define KCSAN_ACCESS_WRITE (1 << 0) /* Access is a write. */
19 #define KCSAN_ACCESS_ATOMIC (1 << 2) /* Access is atomic. */
21 #define KCSAN_ACCESS_ASSERT (1 << 3) /* Access is an assertion. */
22 #define KCSAN_ACCESS_SCOPED (1 << 4) /* Access is a scoped access. */
27 * to validate access to an address. Never use these in header files!
31 * __kcsan_check_access - check generic access for races
33 * @ptr: address of access
34 * @size: size of access
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/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
7 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
16 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
25 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
34 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
43 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
7 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
16 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
25 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
34 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
43 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
[all …]
/openbmc/linux/tools/testing/selftests/bpf/verifier/
H A Ddirect_value_access.c2 "direct map access, write test 1",
14 "direct map access, write test 2",
26 "direct map access, write test 3",
38 "direct map access, write test 4",
50 "direct map access, write test 5",
62 "direct map access, write test 6",
75 "direct map access, write test 7",
87 "direct map access, write test 8",
99 "direct map access, write test 9",
108 .errstr = "invalid access to map value pointer",
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H A Dctx_skb.c2 "access skb fields ok",
33 "access skb fields bad1",
38 .errstr = "invalid bpf_context access",
42 "access skb fields bad2",
63 "access skb fields bad3",
85 "access skb fields bad4",
108 "invalid access __sk_buff family",
114 .errstr = "invalid bpf_context access",
118 "invalid access __sk_buff remote_ip4",
124 .errstr = "invalid bpf_context access",
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
146 * - Step by 8 for 64 bit access.
148 * Note: When performing 32 and 64 bit access, only the low
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json486 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
494 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
502 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
510 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
518 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
526 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
534 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
542 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
550 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
558 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
[all …]
/openbmc/u-boot/drivers/spi/
H A DKconfig12 the SPI uclass. Drivers provide methods to access the SPI
32 access the SPI NOR flash on platforms embedding this Altera
41 used to access the SPI NOR flash on boards using the Aspeed
55 used to access the SPI flash on AE3XX and AE250 platforms embedding
63 to access SPI NOR flash and other SPI peripherals. This driver
72 many AT91 (ARM) chips. This driver can be used to access
80 access the SPI NOR flash on platforms embedding this Broadcom
88 access the SPI NOR flash on platforms embedding these Broadcom
95 be used to access the SPI flash on platforms embedding this
102 used to access the SPI NOR flash on platforms embedding this
[all …]
/openbmc/u-boot/doc/
H A DREADME.unaligned-memory-access.txt8 when it comes to memory access. This document presents some details about
13 The definition of an unaligned access
20 access.
22 The above may seem a little vague, as memory access can happen in different
26 which will compile to multiple-byte memory access instructions, namely when
41 of memory access. However, we must consider ALL supported architectures;
46 Why unaligned access is bad
49 The effects of performing an unaligned memory access vary from architecture
56 happen. The exception handler is able to correct the unaligned access,
60 unaligned access to be corrected.
[all …]
/openbmc/linux/Documentation/core-api/
H A Dunaligned-memory-access.rst14 when it comes to memory access. This document presents some details about
19 The definition of an unaligned access
26 access.
28 The above may seem a little vague, as memory access can happen in different
32 which will compile to multiple-byte memory access instructions, namely when
47 of memory access. However, we must consider ALL supported architectures;
52 Why unaligned access is bad
55 The effects of performing an unaligned memory access vary from architecture
62 happen. The exception handler is able to correct the unaligned access,
66 unaligned access to be corrected.
[all …]
/openbmc/hiomapd/vpnor/
H A DREADME.md7 Enabling the feature virtualises both the host's access to the flash (the mbox
8 protocol), and the BMC's access to the flash (via some filesystem on top of the
28 1. The FFS ToC defines the set of valid access ranges in terms of partitions
31 4. Read access to valid ranges must be granted
32 5. Write access to valid ranges may be granted
33 6. Access ranges that are valid may map into a backing file associated with the
35 7. A read of a valid access range that maps into the backing file will render
37 8. A read of a valid access range that does not map into the backing file will
39 9. A read of an invalid access range will appear erased
40 10. A write to a valid access range that maps into the backing file will update
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