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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_blocks.h21 #define PCI_RD_REGULATOR_SECTION 0x1000
30 #define MME1_RD_REGULATOR_SECTION 0x1000
39 #define MME2_RD_REGULATOR_SECTION 0x1000
48 #define MME3_RD_REGULATOR_SECTION 0x1000
57 #define MME_QM_SECTION 0x1000
60 #define MME_CMDQ_SECTION 0x1000
63 #define ACC_MS_ECC_MEM_0_SECTION 0x1000
66 #define ACC_MS_ECC_MEM_1_SECTION 0x1000
69 #define ACC_MS_ECC_MEM_2_SECTION 0x1000
72 #define ACC_MS_ECC_MEM_3_SECTION 0x1000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h23 #define MME0_SBAB_SECTION 0x1000
188 #define MME1_SBAB_SECTION 0x1000
353 #define MME2_SBAB_SECTION 0x1000
518 #define MME3_SBAB_SECTION 0x1000
680 #define SRAM_Y0_X0_BANK_SECTION 0x1000
686 #define SRAM_Y0_X1_BANK_SECTION 0x1000
692 #define SRAM_Y0_X2_BANK_SECTION 0x1000
698 #define SRAM_Y0_X3_BANK_SECTION 0x1000
704 #define SRAM_Y0_X4_BANK_SECTION 0x1000
710 #define SRAM_Y0_X5_BANK_SECTION 0x1000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
26 #define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
29 #define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
30 #define DCORE0_TPC0_EML_CTI_SECTION 0x1000
32 #define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
[all …]
/openbmc/linux/sound/soc/qcom/
H A Dlpass-sc7280.c256 .i2sctrl_reg_base = 0x1000,
257 .i2sctrl_reg_stride = 0x1000,
260 .irq_reg_stride = 0x1000,
263 .rdma_reg_stride = 0x1000,
266 .rxtx_rdma_reg_stride = 0x1000,
269 .hdmi_rdma_reg_stride = 0x1000,
273 .wrdma_reg_stride = 0x1000,
277 .rxtx_irq_reg_stride = 0x1000,
280 .rxtx_wrdma_reg_stride = 0x1000,
284 .va_wrdma_reg_stride = 0x1000,
[all …]
H A Dlpass-sc7180.c183 .i2sctrl_reg_base = 0x1000,
184 .i2sctrl_reg_stride = 0x1000,
187 .irq_reg_stride = 0x1000,
190 .rdma_reg_stride = 0x1000,
193 .hdmi_rdma_reg_stride = 0x1000,
197 .wrdma_reg_stride = 0x1000,
201 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
202 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
203 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
204 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
[all …]
H A Dlpass-apq8016.c227 .i2sctrl_reg_base = 0x1000,
228 .i2sctrl_reg_stride = 0x1000,
231 .irq_reg_stride = 0x1000,
234 .rdma_reg_stride = 0x1000,
238 .wrdma_reg_stride = 0x1000,
241 .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
242 .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
243 .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
244 .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
245 .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi193 reg = <0x0 0x1000>;
197 reg = <0x1000 0x1000 0x1002000 0x10000>;
201 reg = <0x2000 0x1000>;
205 reg = <0x8000 0x1000 0x1A000 0x1000>;
209 reg = <0x9000 0x1000>;
213 reg = <0x11000 0x1000>;
218 reg = <0x12000 0x1000>;
223 reg = <0x13000 0x1000>;
228 reg = <0x14000 0x1000>;
232 reg = <0x18000 0x1000>;
[all …]
H A Dinterlaken-lac-portals.dtsi40 reg = <0x0 0x1000>;
45 reg = <0x1000 0x1000>;
50 reg = <0x2000 0x1000>;
55 reg = <0x3000 0x1000>;
60 reg = <0x4000 0x1000>;
65 reg = <0x5000 0x1000>;
70 reg = <0x6000 0x1000>;
75 reg = <0x7000 0x1000>;
80 reg = <0x8000 0x1000>;
85 reg = <0x9000 0x1000>;
[all …]
H A Db4si-post.dtsi96 reg = <0x0 0x1000>;
100 reg = <0x1000 0x1000 0x1002000 0x10000>;
104 reg = <0x2000 0x1000>;
108 reg = <0x8000 0x1000 0x1A000 0x1000>;
112 reg = <0x9000 0x1000>;
116 reg = <0x11000 0x1000>;
121 reg = <0x12000 0x1000>;
125 reg = <0x18000 0x1000>;
129 reg = <0x22000 0x1000>;
133 reg = <0x30000 0x1000 0x1022000 0x10000>;
[all …]
H A Dt2081si-post.dtsi177 reg = <0x0 0x1000>;
181 reg = <0x1000 0x1000 0x1002000 0x10000>;
185 reg = <0x2000 0x1000>;
189 reg = <0x8000 0x1000 0x1A000 0x1000>;
193 reg = <0x11000 0x1000>;
198 reg = <0x12000 0x1000>;
202 reg = <0x18000 0x1000>;
206 reg = <0x22000 0x1000>;
210 reg = <0x30000 0x1000 0x1022000 0x10000>;
214 reg = <0x31000 0x1000 0x1042000 0x10000>;
[all …]
H A Db4860si-post.dtsi79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
123 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
128 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
133 reg = <0x48000 0x4000>, <0x1012000 0x1000>;
138 reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h259 #define MM_PMC_CFU_STREAM_SIZE 0x1000
261 #define MM_PMC_CFU_SFR_SIZE 0x1000
263 #define MM_PMC_CFU_FDRO_SIZE 0x1000
268 #define MM_PMC_CFRAME0_REG_SIZE 0x1000
270 #define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
272 #define MM_PMC_CFRAME1_REG_SIZE 0x1000
274 #define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
276 #define MM_PMC_CFRAME2_REG_SIZE 0x1000
278 #define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
280 #define MM_PMC_CFRAME3_REG_SIZE 0x1000
[all …]
H A Dfsl-imx6.h157 #define FSL_IMX6_PTF_CTRL_SIZE 0x1000
159 #define FSL_IMX6_PTM3_SIZE 0x1000
161 #define FSL_IMX6_PTM2_SIZE 0x1000
163 #define FSL_IMX6_PTM1_SIZE 0x1000
165 #define FSL_IMX6_PTM0_SIZE 0x1000
167 #define FSL_IMX6_CTI3_SIZE 0x1000
169 #define FSL_IMX6_CTI2_SIZE 0x1000
171 #define FSL_IMX6_CTI1_SIZE 0x1000
173 #define FSL_IMX6_CTI0_SIZE 0x1000
175 #define FSL_IMX6_CPU3_PMU_SIZE 0x1000
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D05874 $QEMU_IO -c 'write -P 0xa 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
75 $QEMU_IO -c 'write -P 0xb 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c 'write -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
78 $QEMU_IO -c 'write -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
83 $QEMU_IO -c 'read -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
84 $QEMU_IO -c 'read -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
90 $QEMU_IO_NBD -r -c 'read -P 0xa 0x1000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
91 $QEMU_IO_NBD -r -c 'read -P 0xb 0x2000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
97 $QEMU_IO_NBD -r -c 'read -P 0xa 0x1000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
98 $QEMU_IO_NBD -r -c 'read -P 0xb 0x2000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
9 compatible = "ingenic,x1000", "ingenic,x1000e";
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
54 cgu: x1000-cgu@10000000 {
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
67 compatible = "ingenic,x1000-phy";
78 compatible = "ingenic,x1000-rng";
91 compatible = "ingenic,x1000-ost";
104 compatible = "ingenic,x1000-tcu", "simple-mfd";
[all …]
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhisi-x5hd2.dtsi23 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
41 reg = <0x00002000 0x1000>;
55 reg = <0x00a29000 0x1000>;
64 reg = <0x00a2a000 0x1000>;
73 reg = <0x00a2b000 0x1000>;
82 reg = <0x00a81000 0x1000>;
91 reg = <0x00b00000 0x1000>;
100 reg = <0x00006000 0x1000>;
109 reg = <0x00b02000 0x1000>;
118 reg = <0x00b03000 0x1000>;
[all …]
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc65 XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, 0, 0, 0, 0, 0, 0)
66 XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, 0, 0, 0, 0, 0, 0)
77 XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, 0, 0, 0, 0, 0, 0)
78 XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, 0, 0, 0, 0, 0, 0)
79 XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, 0, 0, 0, 0, 0, 0)
80 XTREG(55, 220, 25, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, 0, 0, 0, 0, 0, 0)
81 XTREG(56, 224, 25, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, 0, 0, 0, 0, 0, 0)
82 XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, 0, 0, 0, 0, 0, 0)
83 XTREG(58, 232, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, 0, 0, 0, 0, 0, 0)
84 XTREG(59, 236, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, 0, 0, 0, 0, 0, 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi84 reg = <0xa9000000 0x1000>;
89 reg = <0xb0000000 0x1000>;
97 reg = <0xb4000000 0x1000>;
104 reg = <0xc0000000 0x1000>;
118 reg = <0xc4000000 0x1000>;
123 reg = <0xc8010000 0x1000>;
127 reg = <0xcc000000 0x1000>;
139 reg = <0x90000000 0x1000>;
146 reg = <0x90010000 0x1000>;
151 reg = <0x90020000 0x1000>;
[all …]
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc102 XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176,
104 XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208,
126 XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr,
128 XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid,
130 XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid,
132 XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg,
134 XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg,
136 XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable,
138 XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr,
140 XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0,
[all …]
/openbmc/linux/arch/arm64/boot/dts/lg/
H A Dlg1312.dtsi68 reg = <0x0 0xc0001000 0x1000>,
116 reg = <0x0 0xc1b00000 0x1000>;
136 reg = <0x0 0xfd100000 0x1000>;
143 reg = <0x0 0xfd200000 0x1000>;
150 reg = <0x0 0xfe000000 0x1000>;
158 reg = <0x0 0xfe100000 0x1000>;
166 reg = <0x0 0xfe200000 0x1000>;
174 reg = <0x0 0xfe800000 0x1000>;
181 reg = <0x0 0xfe900000 0x1000>;
188 reg = <0x0 0xc1128000 0x1000>;
[all …]
H A Dlg1313.dtsi68 reg = <0x0 0xc0001000 0x1000>,
116 reg = <0x0 0xc3700000 0x1000>;
136 reg = <0x0 0xfd100000 0x1000>;
143 reg = <0x0 0xfd200000 0x1000>;
150 reg = <0x0 0xfe000000 0x1000>;
158 reg = <0x0 0xfe100000 0x1000>;
166 reg = <0x0 0xfe200000 0x1000>;
174 reg = <0x0 0xfe800000 0x1000>;
181 reg = <0x0 0xfe900000 0x1000>;
188 reg = <0x0 0xc1128000 0x1000>;
[all …]
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc42 XTREG( 19, 76,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
43 XTREG( 20, 80,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
45 XTREG( 22, 88,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
46 XTREG( 23, 92, 1, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
47 XTREG( 24, 96,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
48 XTREG( 25,100,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
49 XTREG( 26,104,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
50 XTREG( 27,108,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
51 XTREG( 28,112,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
52 XTREG( 29,116,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear600.dtsi35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
88 reg = <0xfc000000 0x1000>;
96 reg = <0xe1800000 0x1000>;
104 reg = <0xe2000000 0x1000>;
112 reg = <0xe1900000 0x1000>;
120 reg = <0xe2100000 0x1000>;
[all …]

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