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/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S40 #define X __HVM_PDE_S_INVALID macro
47 .word X,X,X,X
48 .word X,X,X,X
49 .word X,X,X,X
50 .word X,X,X,X
51 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
52 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
53 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
54 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
55 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dcrct10dif-vpmsum_asm.S21 /* x^261184 mod p(x), x^261120 mod p(x) */
24 /* x^260160 mod p(x), x^260096 mod p(x) */
27 /* x^259136 mod p(x), x^259072 mod p(x) */
30 /* x^258112 mod p(x), x^258048 mod p(x) */
33 /* x^257088 mod p(x), x^257024 mod p(x) */
36 /* x^256064 mod p(x), x^256000 mod p(x) */
39 /* x^255040 mod p(x), x^254976 mod p(x) */
42 /* x^254016 mod p(x), x^253952 mod p(x) */
45 /* x^252992 mod p(x), x^252928 mod p(x) */
48 /* x^251968 mod p(x), x^251904 mod p(x) */
[all …]
H A Dcrc32c-vpmsum_asm.S17 /* x^261120 mod p(x)` << 1, x^261184 mod p(x)` << 1 */
20 /* x^260096 mod p(x)` << 1, x^260160 mod p(x)` << 1 */
23 /* x^259072 mod p(x)` << 1, x^259136 mod p(x)` << 1 */
26 /* x^258048 mod p(x)` << 1, x^258112 mod p(x)` << 1 */
29 /* x^257024 mod p(x)` << 1, x^257088 mod p(x)` << 1 */
32 /* x^256000 mod p(x)` << 1, x^256064 mod p(x)` << 1 */
35 /* x^254976 mod p(x)` << 1, x^255040 mod p(x)` << 1 */
38 /* x^253952 mod p(x)` << 1, x^254016 mod p(x)` << 1 */
41 /* x^252928 mod p(x)` << 1, x^252992 mod p(x)` << 1 */
44 /* x^251904 mod p(x)` << 1, x^251968 mod p(x)` << 1 */
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes_regs.h35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
47 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h15 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) argument
16 #define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) argument
359 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) argument
360 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) argument
361 #define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) argument
362 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) argument
363 #define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) argument
364 #define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) argument
365 #define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) argument
366 #define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) argument
[all …]
/openbmc/qemu/hw/intc/
H A Dtrace-events7 pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr 0x%"PRIx64" val 0x%"PRIx…
8 pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"PRIx64" val 0x%x"
11 cpu_set_apic_base(uint64_t val) "0x%016"PRIx64
12 cpu_get_apic_base(uint64_t val) "0x%016"PRIx64
17 apic_register_read(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
18 apic_register_write(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
25 …nt8_t size, uint32_t val) "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retv…
26 …int8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" va…
35 …io_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0x%x"
36 …_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = 0x%x"
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
[all …]
H A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
H A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
[all …]
H A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
[all …]
H A Dr300d.h70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
[all …]
H A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
/openbmc/u-boot/include/synopsys/
H A Ddwcddr21mctl.h47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
53 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
54 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
55 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument
56 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument
82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
[all …]
/openbmc/u-boot/include/andestech/
H A Dandes_pcu.h79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
99 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
[all …]
/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
[all …]
/openbmc/linux/lib/crypto/
H A Dchacha.c16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/openbmc/qemu/hw/ppc/
H A Dtrace-events4 spapr_pci_msi(const char *msg, uint32_t ca) "%s (cfg=0x%x)"
5 spapr_pci_msi_setup(const char *name, unsigned vector, uint64_t addr) "dev\"%s\" vector %u, addr=0x…
6 …e_msi(unsigned cfg, unsigned func, unsigned req, unsigned first) "cfgaddr 0x%x func %u, requested …
8 spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq) "@0x%"PRIx64"<=0x%"PRIx64" IRQ %…
10 …signed config_addr, unsigned req_num, unsigned max_irqs) "Guest device at 0x%x asked %u, have only…
14 …int32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=0x%x, explicit_match=%u, new=0x%x"
15 spapr_h_resize_hpt_prepare(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64
16 spapr_h_resize_hpt_commit(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64
18 …(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x"
19 …(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x"
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dregs.h36 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
40 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
44 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
48 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
52 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
56 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
61 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
62 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
65 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
69 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dregs.h5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
13 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
21 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
26 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
30 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
33 #define V_FLMODE(x) ((x) << S_FLMODE) argument
38 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
41 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D013.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D022.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
/openbmc/linux/tools/memory-model/
H A Dlinux-kernel.def9 READ_ONCE(X) __load{once}(X)
10 WRITE_ONCE(X,V) { __store{once}(X,V); }
13 smp_store_release(X,V) { __store{release}(*X,V); }
14 smp_load_acquire(X) __load{acquire}(*X)
15 rcu_assign_pointer(X,V) { __store{release}(X,V); }
16 rcu_dereference(X) __load{once}(X)
17 smp_store_mb(X,V) { __store{once}(X,V); __fence{mb}; }
31 xchg(X,V) __xchg{mb}(X,V)
32 xchg_relaxed(X,V) __xchg{once}(X,V)
33 xchg_release(X,V) __xchg{release}(X,V)
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ argument
39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument
41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument
50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ argument
54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
[all …]
/openbmc/qemu/hw/usb/
H A Dtrace-events17 usb_ohci_iso_td_read_failed(uint32_t addr) "ISO_TD read error at 0x%x"
18 …_TD ED head 0x%.8x tailp 0x%.8x, flags 0x%.8x bp 0x%.8x next 0x%.8x be 0x%.8x, frame_number 0x%.8x…
19 …2_t o4, uint32_t o5, uint32_t o6, uint32_t o7) "0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0…
23 usb_ohci_iso_td_bad_bp_be(uint32_t bp, uint32_t be) "ISO_TD bp 0x%.8x be 0x%.8x"
24 …iso_td_bad_cc_not_accessed(uint32_t start, uint32_t next) "ISO_TD cc != not accessed 0x%.8x 0x%.8x"
25 …_td_bad_cc_overrun(uint32_t start, uint32_t next) "ISO_TD start_offset=0x%.8x > next_offset=0x%.8x"
26 …_t s, uint32_t e, const char *str, ssize_t len, int ret) "0x%.8x eo 0x%.8x sa 0x%.8x ea 0x%.8x dir…
31 …hci_td_bad_pid(const char *s, uint32_t edf, uint32_t tdf) "Bad pid %s: ed.flags 0x%x td.flags 0x%x"
32 usb_ohci_td_bad_buf(uint32_t cbp, uint32_t be) "Bad cbp = 0x%x > be = 0x%x"
43 usb_ohci_set_ctl(const char *s, uint32_t new_state) "%s: new state 0x%x"
[all …]

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