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/openbmc/linux/sound/drivers/
H A Dserial-u16550.c157 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
159 if (!uart->timer_running) { in snd_uart16550_add_timer()
161 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
162 uart->timer_running = 1; in snd_uart16550_add_timer()
166 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
168 if (uart->timer_running) { in snd_uart16550_del_timer()
169 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
170 uart->timer_running = 0; in snd_uart16550_del_timer()
175 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
177 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
[all …]
/openbmc/qemu/hw/char/
H A Dgrlib_apbuart.c2 * QEMU GRLIB APB UART Emulator
41 /* UART status register fields */
54 /* UART control register fields */
79 OBJECT_DECLARE_SIMPLE_TYPE(UART, GRLIB_APB_UART)
81 struct UART { struct
99 static int uart_data_to_read(UART *uart) in uart_data_to_read() argument
101 return uart->current < uart->len; in uart_data_to_read()
104 static char uart_pop(UART *uart) in uart_pop() argument
108 if (uart->len == 0) { in uart_pop()
109 uart->status &= ~UART_DATA_READY; in uart_pop()
[all …]
/openbmc/u-boot/drivers/serial/
H A DKconfig12 meaning of either setting the baudrate for the early debug UART
32 In various cases, we need to specify which of the UART devices that
41 In very space-constrained devices even the full UART driver is too
42 large. In this case the debug UART can still be used in some cases.
43 This option enables the full UART in U-Boot, so if is it disabled,
44 the full UART driver will be omitted, thus saving space.
51 In very space-constrained devices even the full UART driver is too
52 large. In this case the debug UART can still be used in some cases.
53 This option enables the full UART in SPL, so if is it disabled,
54 the full UART driver will be omitted, thus saving space.
[all …]
H A Dmcfuart.c11 * Minimal serial functions needed to use one of the uart ports
21 #include <asm/uart.h>
27 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) in mcf_serial_init_common() argument
33 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in mcf_serial_init_common()
34 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
35 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
37 writeb(UART_UCR_RESET_MR, &uart->ucr); in mcf_serial_init_common()
40 writeb(0, &uart->uimr); in mcf_serial_init_common()
43 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in mcf_serial_init_common()
[all …]
H A Dserial_s5p.c17 #include <asm/arch/uart.h>
33 u8 port_id; /* uart port number */
62 static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) in s5p_serial_init() argument
65 writel(0x3, &uart->ufcon); in s5p_serial_init()
66 writel(0, &uart->umcon); in s5p_serial_init()
68 writel(0x3, &uart->ulcon); in s5p_serial_init()
70 writel(0x245, &uart->ucon); in s5p_serial_init()
73 static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, in s5p_serial_baud() argument
80 writel(val / 16 - 1, &uart->ubrdiv); in s5p_serial_baud()
83 writew(udivslot[val % 16], &uart->rest.slot); in s5p_serial_baud()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmediatek,uart.yaml4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6580-uart
29 - mediatek,mt6582-uart
30 - mediatek,mt6589-uart
31 - mediatek,mt6755-uart
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H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
23 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
24 respectively the UART sum interrupt, the UART TX interrupt and
[all …]
H A Damlogic,meson-uart.yaml5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
31 - amlogic,meson6-uart
32 - amlogic,meson8-uart
33 - amlogic,meson8b-uart
34 - amlogic,meson-gx-uart
35 - amlogic,meson-s4-uart
36 - amlogic,meson-a1-uart
[all …]
H A Dsnps-dw-apb-uart.yaml4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk1808-uart
27 - rockchip,rk3036-uart
28 - rockchip,rk3066-uart
29 - rockchip,rk3128-uart
[all …]
H A Dfsl-imx-uart.yaml4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
23 - fsl,imx25-uart
24 - fsl,imx27-uart
25 - fsl,imx31-uart
26 - fsl,imx35-uart
27 - fsl,imx50-uart
28 - fsl,imx51-uart
[all …]
H A Dsamsung_uart.yaml7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - const: samsung,exynosautov9-uart
23 - const: samsung,exynos850-uart
25 - apple,s5l-uart
26 - axis,artpec8-uart
27 - samsung,s3c2410-uart
28 - samsung,s3c2412-uart
29 - samsung,s3c2440-uart
30 - samsung,s3c6400-uart
[all …]
H A D8250.yaml7 title: UART (Universal Asynchronous Receiver/Transmitter)
30 const: mrvl,mmp-uart
62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
82 - nxp,lpc1850-uart
84 - ti,da830-uart
[all …]
H A Dsprd-uart.yaml5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
8 title: Spreadtrum serial UART
20 - sprd,sc9860-uart
21 - sprd,sc9863a-uart
22 - sprd,ums512-uart
23 - const: sprd,sc9836-uart
24 - const: sprd,sc9836-uart
38 "enable" for UART module enable clock, "uart" for UART clock, "source"
39 for UART source (parent) clock.
42 - const: uart
[all …]
H A Dbrcm,bcm7271-uart.yaml4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dmen_z135_uart.c3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
[all …]
H A Dtimbuart.c3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
118 struct timbuart_port *uart = in timbuart_handle_tx_port() local
137 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
174 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
177 spin_lock(&uart->port.lock); in timbuart_tasklet()
179 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
180 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
[all …]
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_tegra.c46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
91 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
92 if (IS_ERR(uart->rst)) in tegra_uart_probe()
93 return PTR_ERR(uart->rst); in tegra_uart_probe()
97 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
98 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
103 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
107 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
[all …]
H A D8250_core.c277 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
278 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
610 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
654 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
655 * console=uart[8250],0x<addr>[,<options>]
667 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
836 struct uart_8250_port uart; in serial8250_probe() local
839 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
845 uart.port.iobase = p->iobase; in serial8250_probe()
846 uart.port.membase = p->membase; in serial8250_probe()
[all …]
H A D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
93 struct uart_8250_port uart; in lpc18xx_serial_probe() local
107 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
109 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
111 if (!uart.port.membase) in lpc18xx_serial_probe()
120 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
138 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
144 uart.port.line = ret; in lpc18xx_serial_probe()
149 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
150 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
[all …]
H A D8250_ingenic.c6 * Ingenic SoC UART support
142 * oscillator and some peripherals including UART, which will in jz4750_early_console_setup()
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
177 /* UART module enable */ in ingenic_uart_serial_out()
233 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
[all …]
/openbmc/linux/include/uapi/linux/
H A Dserial_core.h33 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
34 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
35 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
36 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
37 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
38 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
39 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
43 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
44 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
45 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
/openbmc/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c16 #include <asm/uart.h>
90 uart_t *uart; in rs_serial_init() local
95 uart = (uart_t *)(MMAP_UART0); in rs_serial_init()
98 uart = (uart_t *)(MMAP_UART1); in rs_serial_init()
101 uart = (uart_t *)(MMAP_UART2); in rs_serial_init()
104 uart = (uart_t *)(MMAP_UART0); in rs_serial_init()
109 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in rs_serial_init()
110 writeb(UART_UCR_RESET_RX, &uart->ucr); in rs_serial_init()
111 writeb(UART_UCR_RESET_TX, &uart->ucr); in rs_serial_init()
112 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in rs_serial_init()
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
/openbmc/openbmc/meta-bytedance/meta-g220a/recipes-phosphor/console/obmc-console/
H A Dobmc-console@.service7 …/bin/sh -c 'echo -n "uart3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
8 …/bin/sh -c 'echo -n "uart1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
9 …e=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
10 …/bin/sh -c 'echo -n "uart4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
12 …t=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
13 …t=/bin/sh -c 'echo -n "io3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
14 …t=/bin/sh -c 'echo -n "io4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…
15 …/bin/sh -c 'echo -n "uart1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart-routing/…

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