| /openbmc/qemu/hw/timer/ |
| H A D | pxa2xx_timer.c | 169 /* fall through */ in pxa2xx_timer_read()
171 /* fall through */ in pxa2xx_timer_read()
173 /* fall through */ in pxa2xx_timer_read()
177 /* fall through */ in pxa2xx_timer_read()
179 /* fall through */ in pxa2xx_timer_read()
181 /* fall through */ in pxa2xx_timer_read()
183 /* fall through */ in pxa2xx_timer_read()
185 /* fall through */ in pxa2xx_timer_read()
187 /* fall through */ in pxa2xx_timer_read()
189 /* fall through */ in pxa2xx_timer_read()
[all …]
|
| /openbmc/linux/arch/m68k/ifpsp060/ |
| H A D | fpsp.doc | 109 The third section is the code section. After entering through an "Entry-point",
173 always exits through _060_real_snan <----
181 always exits through _060_real_operr <-----
189 always exits through _060_real_dz <----
197 always exits through _060_real_inex <----
206 may exit through _060_real_inex <---|
208 may exit through _060_real_ovfl <---|
210 may exit through _060_fpsp_done <---|
218 may exit through _060_real_inex <---|
220 may exit through _060_real_unfl <---|
[all …]
|
| H A D | isp.doc | 118 The third section is the code section. After entering through an "Entry-point",
176 060ISP is installed properly, these instructions will enter through the
185 through the "Entry-point"s _060_isp_cas() or _060_isp_cas2().
195 code has completed, then it should re-enter the 060ISP package through the
198 _060_real_cas2() and what it should be upon return to the package through
212 may exit through _060_real_itrace <----|
214 may exit through _060_real_chk <----|
216 may exit through _060_real_divbyzero <----|
218 may exit through _060_isp_done <----|
|
| /openbmc/openbmc-test-automation/openpower/ras/ |
| H A D | ras_utils.robot | 2 Documentation Utility for RAS test scenarios through HOST & BMC.
47 [Documentation] Inject and verify recoverable error on processor through
51 ... (e.g: Processor core, CAPP, MCA) through BMC/HOST.
58 # interface_type Inject error through 'BMC' or 'HOST'.
65 Run Keyword Inject Error Through ${interface_type}
75 [Documentation] Inject and verify unrecoverable error on processor through
79 ... (e.g: Processor core, CAPP, MCA) through BMC/HOST.
87 # interface_type Inject error through 'BMC' or 'HOST'.
96 Run Keyword Inject Error Through ${interface_type}
125 [Documentation] Fetch FIR address translation value through HOST.
[all …]
|
| /openbmc/qemu/ui/ |
| H A D | win32-kbd-hook.c | 29 /* fall through */ in keyboard_hook_cb()
31 /* fall through */ in keyboard_hook_cb()
33 /* fall through */ in keyboard_hook_cb()
35 /* fall through */ in keyboard_hook_cb()
37 /* fall through */ in keyboard_hook_cb()
39 /* fall through */ in keyboard_hook_cb()
41 /* fall through */ in keyboard_hook_cb()
|
| /openbmc/u-boot/board/work-microwave/work_92105/ |
| H A D | README | 5 - 1 GB SLC NAND, managed through MLC controller.
13 - SPI (through SSP interface)
16 through the port expander and DACs
25 This file can be loaded in SRAM through a JTAG
26 debugger or through the LPC32XX Service Boot
30 DDR through a JTAG debugger (for instance by
32 U-Boot through e.g. 'loady' or 'tftp' and then
36 SPL assumes (even when loaded through JTAG or
|
| /openbmc/openbmc-test-automation/lib/ras/ |
| H A D | host_utils.robot | 2 Documentation Utility for error injection scenarios through HOST & BMC.
85 FIR Address Translation Through HOST
86 [Documentation] Do FIR address translation through host for given FIR,
102 Inject Error Through HOST
104 ... CPU/CME/OCC/NPU/CAPP/MCA etc. through HOST.
137 [Documentation] Inject UE MCACALFIR checkstop on processor through
140 Inject Error Through HOST 05010800 4000000000000000 1
142 Disable CPU States Through HOST
143 [Documentation] Disable CPU states through host.
177 Inject Error Through BMC
[all …]
|
| /openbmc/linux/Documentation/driver-api/md/ |
| H A D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported
11 in write-through mode. A user can switch it to write-back mode by::
15 And switch it back to write-through mode by::
17 echo "write-through" > /sys/block/md0/md/journal_mode
22 write-through mode
34 The write-through cache will cache all data on cache disk first. After the data
39 In write-through mode, MD reports IO completion to upper layer (usually
44 In write-through mode, the cache disk isn't required to be big. Several
80 The write-through and write-back cache use the same disk format. The cache disk
91 write-through mode, MD calculates parity for IO data, writes both IO data and
|
| /openbmc/linux/Documentation/driver-api/media/drivers/ |
| H A D | pvrusb2.rst | 84 interfaces tie into the driver through this module. This module
86 and is designed to allow concurrent access through multiple
88 the tuner's frequency through sysfs while simultaneously streaming
89 video through V4L out to an instance of mplayer).
109 (proxy through USB instead of PCI) are enough different that this
116 access to the driver should be through one of the high level
123 will work through here.
151 kernel-friendly I2C adaptor driver, through which other external
154 through here that other V4L modules can reach into this driver to
158 through one of the high level interfaces).
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,pruss-intc.yaml | 15 which are then mapped to 10 possible output interrupts through two levels
19 remaining 8 (2 through 9) connected to external interrupt controllers
23 differences on the output interrupts 2 through 9. If this property is not
24 defined, it implies that all the PRUSS INTC output interrupts 2 through 9
25 (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
30 through 19) are connected to new sub-modules within the ICSSG instances.
81 interrupts through 2 levels of many-to-one mapping i.e. events to channel
82 mapping and channels to host interrupts so through this property entire
89 output interrupts 2 through 9) that are not connected to the Arm interrupt
|
| /openbmc/linux/Documentation/networking/ |
| H A D | representors.rst | 104 if) their network access is implemented through a virtual switch port. [#]_
110 through a virtual switch port, even if they do not have a corresponding PCIe
113 This allows the entire switching behaviour of the NIC to be controlled through
120 A PCIe function which does not have network access through the internal switch
121 (not even indirectly through the hardware implementation of whatever services
131 network packets pass through the virtual port onto the switch. The network
132 access that the IP stack "sees" would then be configurable through tc rules;
154 through the switchdev function. For example, ``ndo_start_xmit()`` might send
155 the packet through a hardware TX queue attached to the switchdev function, with
163 through ``net_dev->dev.parent`` / ``SET_NETDEV_DEV()``), either of the
[all …]
|
| /openbmc/linux/arch/xtensa/include/asm/ |
| H A D | asm-uaccess.h | 31 * <error>. This implies that the macro falls through to the next
36 * through on success).
42 * <error> label to branch to on error; implies fall-through
61 * <error>. This implies that the macro falls through to the next
65 * branch fall-through case on success.
72 * <error> label to branch to on error; implies fall-through
|
| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 7 devices in the system can only support go through vIOMMU or not, which
9 coexist of devices go through vIOMMU and devices not. This is useful to
10 passthrough devices with no-iommu mode and devices go through vIOMMU in
18 the attached devices will go through vIOMMU by default.
47 - a pxb host bridge which go through SMMUv3
61 - a pxb host bridge which go through iommu
88 so that the devices will by default go through iommu if there exist one.
|
| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_rvzce.c.inc | 128 /* FALL THROUGH */
131 /* FALL THROUGH */
134 /* FALL THROUGH */
137 /* FALL THROUGH */
140 /* FALL THROUGH */
143 /* FALL THROUGH */
146 /* FALL THROUGH */
149 /* FALL THROUGH */
152 /* FALL THROUGH */
155 /* FALL THROUGH */
[all …]
|
| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | e300.h | 85 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
86 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
87 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
88 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
89 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
|
| /openbmc/linux/sound/core/seq/ |
| H A D | seq_dummy.c | 3 * ALSA sequencer MIDI-through client
17 Sequencer MIDI-through client
19 This gives a simple midi-through client. All the normal input events
49 MODULE_DESCRIPTION("ALSA sequencer MIDI-through client");
122 sprintf(pinfo.name, "Midi Through Port-%d:%c", idx, in create_port()
125 sprintf(pinfo.name, "Midi Through Port-%d", idx); in create_port()
165 "Midi Through"); in register_client()
169 /* don't convert events but just pass-through */ in register_client()
|
| /openbmc/linux/include/linux/mfd/ |
| H A D | db8500-prcmu.h | 306 * through I2C has not been correctly executed in the given time
308 * through I2C has not been correctly executed in the given time
309 * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
312 * through I2C has not been correctly executed in the given time
313 * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
316 * through I2C has not been correctly executed in the given time
317 * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
319 * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
321 * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
323 * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
[all …]
|
| /openbmc/openpower-occ-control/ |
| H A D | occ_pass_through.hpp | 39 /** @brief Ctor to put pass-through d-bus object on the bus
50 /** @brief Pass through command to OCC from dbus
51 * @param[in] command - command to pass-through
56 /** @brief Pass through command to OCC from openpower-occ-control
57 * @param[in] command - command to pass-through
72 /** @brief Pass-through occ path on the bus */
|
| /openbmc/linux/include/uapi/linux/ |
| H A D | if.h | 50 * via /sys/class/net/<dev>/flags. Flags which can be toggled through sysfs
59 * @IFF_UP: interface is up. Can be toggled through sysfs.
61 * @IFF_DEBUG: turn on debugging. Can be toggled through sysfs.
64 * @IFF_NOTRAILERS: avoid use of trailers. Can be toggled through sysfs.
67 * @IFF_NOARP: no ARP protocol. Can be toggled through sysfs. Volatile.
68 * @IFF_PROMISC: receive all packets. Can be toggled through sysfs.
69 * @IFF_ALLMULTI: receive all multicast packets. Can be toggled through
73 * @IFF_MULTICAST: Supports multicast. Can be toggled through sysfs.
74 * @IFF_PORTSEL: can set media type. Can be toggled through sysfs.
75 * @IFF_AUTOMEDIA: auto media select active. Can be toggled through sysfs.
[all …]
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-compressed.rst | 68 through the ``V4L2_CID_STATELESS_H264_DECODE_MODE``
71 required to be passed through the ``V4L2_CID_STATELESS_H264_SPS``,
122 through the ``V4L2_CID_STATELESS_MPEG2_SEQUENCE`` and
124 Quantisation matrices can optionally be specified through the
166 through the ``V4L2_CID_STATELESS_VP8_FRAME`` control.
188 through the ``V4L2_CID_STATELESS_VP9_FRAME`` and
213 through the ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE``
216 through the following controls:
238 through the ``V4L2_CID_STATELESS_FWHT_PARAMS`` control.
268 frame to decode is required to be passed through the
|
| /openbmc/linux/drivers/hwmon/occ/ |
| H A D | Kconfig | 7 tristate "POWER8 OCC through I2C"
15 established through I2C bus.
21 tristate "POWER9 OCC through SBE"
29 established through SBE fifo on an FSI bus.
|
| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | rt5682.txt | 11 - AVDD-supply: phandle to the regulator supplying analog power through the
15 bias through the MICVDD pin. Either MICVDD or VBAT should be present.
17 - VBAT-supply: phandle to the regulator supplying battery power through the
20 - DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
24 and charge pump through the LDO1_IN pin.
|
| /openbmc/linux/arch/parisc/include/uapi/asm/ |
| H A D | ptrace.h | 21 * It can be accessed through PTRACE_PEEKUSR/PTRACE_POKEUSR only.
48 * It can be accessed through PTRACE_GETREGSET with NT_PRSTATUS
49 * and through PTRACE_GETREGS.
73 * It can be accessed through PTRACE_GETREGSET with NT_PRFPREG
74 * and through PTRACE_GETFPREGS.
|
| /openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| H A D | usb.txt | 11 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
15 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
| /openbmc/linux/Documentation/filesystems/ |
| H A D | fuse-io.rst | 11 + write-through
25 write-through mode is the default and is supported on all kernels. The
29 In write-through mode each write is immediately sent to userspace as one or more
39 assumes that all changes to the filesystem go through the FUSE kernel module
|