1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Copyright 2004 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * Liberty Eran (liberty@freescale.com) 4*a47a12beSStefan Roese */ 5*a47a12beSStefan Roese 6*a47a12beSStefan Roese #ifndef __E300_H__ 7*a47a12beSStefan Roese #define __E300_H__ 8*a47a12beSStefan Roese 9*a47a12beSStefan Roese #define PVR_E300C1 0x80830000 10*a47a12beSStefan Roese #define PVR_E300C2 0x80840000 11*a47a12beSStefan Roese #define PVR_E300C3 0x80850000 12*a47a12beSStefan Roese #define PVR_E300C4 0x80860000 13*a47a12beSStefan Roese 14*a47a12beSStefan Roese /* 15*a47a12beSStefan Roese * Hardware Implementation-Dependent Register 0 (HID0) 16*a47a12beSStefan Roese */ 17*a47a12beSStefan Roese 18*a47a12beSStefan Roese /* #define HID0 1008 already defined in processor.h */ 19*a47a12beSStefan Roese #define HID0_MASK_MACHINE_CHECK 0x00000000 20*a47a12beSStefan Roese #define HID0_ENABLE_MACHINE_CHECK 0x80000000 21*a47a12beSStefan Roese 22*a47a12beSStefan Roese #define HID0_DISABLE_CACHE_PARITY 0x00000000 23*a47a12beSStefan Roese #define HID0_ENABLE_CACHE_PARITY 0x40000000 24*a47a12beSStefan Roese 25*a47a12beSStefan Roese #define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ 26*a47a12beSStefan Roese #define HID0_ENABLE_ADDRESS_PARITY 0x20000000 27*a47a12beSStefan Roese 28*a47a12beSStefan Roese #define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ 29*a47a12beSStefan Roese #define HID0_ENABLE_DATE_PARITY 0x10000000 30*a47a12beSStefan Roese 31*a47a12beSStefan Roese #define HID0_CORE_CLK_OUT 0x00000000 32*a47a12beSStefan Roese #define HID0_CORE_CLK_OUT_DIV_2 0x08000000 33*a47a12beSStefan Roese 34*a47a12beSStefan Roese #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ 35*a47a12beSStefan Roese #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 36*a47a12beSStefan Roese 37*a47a12beSStefan Roese #define HID0_DISABLE_DOSE_MODE 0x00000000 38*a47a12beSStefan Roese #define HID0_ENABLE_DOSE_MODE 0x00800000 39*a47a12beSStefan Roese 40*a47a12beSStefan Roese #define HID0_DISABLE_NAP_MODE 0x00000000 41*a47a12beSStefan Roese #define HID0_ENABLE_NAP_MODE 0x00400000 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese #define HID0_DISABLE_SLEEP_MODE 0x00000000 44*a47a12beSStefan Roese #define HID0_ENABLE_SLEEP_MODE 0x00200000 45*a47a12beSStefan Roese 46*a47a12beSStefan Roese #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 47*a47a12beSStefan Roese #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese #define HID0_SOFT_RESET 0x00010000 50*a47a12beSStefan Roese 51*a47a12beSStefan Roese #define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 52*a47a12beSStefan Roese #define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 53*a47a12beSStefan Roese 54*a47a12beSStefan Roese #define HID0_DISABLE_DATA_CACHE 0x00000000 55*a47a12beSStefan Roese #define HID0_ENABLE_DATA_CACHE 0x00004000 56*a47a12beSStefan Roese 57*a47a12beSStefan Roese #define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 58*a47a12beSStefan Roese 59*a47a12beSStefan Roese #define HID0_LOCK_DATA_CACHE 0x00001000 60*a47a12beSStefan Roese 61*a47a12beSStefan Roese #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 62*a47a12beSStefan Roese 63*a47a12beSStefan Roese #define HID0_INVALIDATE_DATA_CACHE 0x00000400 64*a47a12beSStefan Roese 65*a47a12beSStefan Roese #define HID0_DISABLE_M_BIT 0x00000000 66*a47a12beSStefan Roese #define HID0_ENABLE_M_BIT 0x00000080 67*a47a12beSStefan Roese 68*a47a12beSStefan Roese #define HID0_FBIOB 0x00000010 69*a47a12beSStefan Roese 70*a47a12beSStefan Roese #define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 71*a47a12beSStefan Roese #define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 72*a47a12beSStefan Roese 73*a47a12beSStefan Roese #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 74*a47a12beSStefan Roese #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 75*a47a12beSStefan Roese 76*a47a12beSStefan Roese /* 77*a47a12beSStefan Roese * Hardware Implementation-Dependent Register 2 (HID2) 78*a47a12beSStefan Roese */ 79*a47a12beSStefan Roese #define HID2 1011 80*a47a12beSStefan Roese 81*a47a12beSStefan Roese #define HID2_LET 0x08000000 82*a47a12beSStefan Roese #define HID2_HBE 0x00040000 83*a47a12beSStefan Roese #define HID2_IWLCK_000 0x00000000 /* no ways locked */ 84*a47a12beSStefan Roese #define HID2_IWLCK_001 0x00002000 /* way 0 locked */ 85*a47a12beSStefan Roese #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ 86*a47a12beSStefan Roese #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ 87*a47a12beSStefan Roese #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ 88*a47a12beSStefan Roese #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ 89*a47a12beSStefan Roese #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ 90*a47a12beSStefan Roese 91*a47a12beSStefan Roese #endif /* __E300_H__ */ 92