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/openbmc/qemu/docs/
H A Dblock-replication.txt11 for COLO (COarse-grain LOck-stepping) where the Secondary VM is running.
13 where the Secondary VM is not running.
19 consecutive checkpoints. The VM state of the Primary and Secondary VM is
22 the modified disk contents in the Secondary VM must be buffered, and are
25 the Primary disk are asynchronously forwarded to the Secondary node.
31 |Primary Write Requests| |Secondary Write Requests|
46 | Primary Disk | | Secondary Disk |
49 1) Primary write requests will be copied and forwarded to Secondary
51 2) Before Primary write requests are written to Secondary disk, the
52 original sector content will be read from Secondary disk and
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H A DCOLO-FT.txt18 Both primary VM (PVM) and secondary VM (SVM) run in parallel. They receive the
27 The primary node running the PVM, and the secondary node running the SVM
33 primary node, and then forwarded to the secondary node, so that both the PVM
44 Primary Node Secondary Node
47 | Primary VM | +-----------+-----------+ +-----------+------------+ |Secondary VM|
88 Runs on both the primary and secondary nodes, to periodically check platform
90 the heartbeat stops responding, the secondary node will trigger a failover
95 and sends it to secondary VM's which makes sure the context of secondary VM's
101 to make sure the state of VM in Secondary side is always consistent with VM in
105 Delivers packets to Primary and Secondary, and then compare the responses from
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H A Dcolo-proxy.txt24 (except colo-compare). It keep Secondary VM connect normally to
28 packet and drop the queued secondary packet.
32 Primary qemu Secondary qemu
75 same time, copy and forward packet to secondary
78 Secondary:
82 and update TCP checksum, then send to secondary
95 waiting secondary redirect packet to compare it.
97 queued secondary packet, Otherwise send primary packet
107 Secondary:
147 Packets coming from the secondary char dev will be dropped after comparing.
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/openbmc/qemu/target/sparc/
H A Dasi.h129 #define ASI_AIUS 0x11 /* Secondary, user */
131 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
133 #define ASI_S 0x81 /* Secondary, implicit */
135 #define ASI_SNF 0x83 /* Secondary, no fault */
137 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
139 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
148 #define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */
164 #define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */
166 * secondary, user
174 #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
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/openbmc/linux/arch/arm/mach-bcm/
H A Dplatsmp.c33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
120 /* Ensure the write is visible to the secondary core */ in nsp_write_lut()
141 * The ROM code has the secondary cores looping, waiting for an event.
143 * secondary boot register. When a core finds those bits contain its
147 * address back to the secondary boot register, and finally jumps to
151 * - Encode the (hardware) CPU id with the bottom bits of the secondary
153 * - Write that value into the secondary boot register.
154 * - Generate an event to wake up the secondary CPU(s).
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/openbmc/phosphor-dbus-interfaces/
H A Drequirements.md64 associations should be considered to have a "primary" and "secondary" end, which
67 "contained_by" (secondary) the chassis.
93 (ending in '-ing'). The secondary relationship should be a verb with a Past
99 - The `{primary element}` is `{primary association}` the `{secondary element}`.
100 - The `{secondary element}` is `{secondary association}` the
105 `{secondary element}` and `{secondary element}/{secondary association}` with an
109 preposition to the secondary association, such as 'by' or 'with'.
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dasi.h130 #define ASI_AIUS 0x11 /* Secondary, user */
132 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
134 #define ASI_S 0x81 /* Secondary, implicit */
136 #define ASI_SNF 0x83 /* Secondary, no fault */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
161 * secondary, user
231 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
242 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
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/openbmc/linux/certs/
H A Dsystem_keyring.c77 * addition by both built-in and secondary keyrings.
84 * being vouched for by a key in either the built-in or the secondary system
93 /* If we have a secondary trusted keyring, then that contains a link in restrict_link_by_builtin_and_secondary_trusted()
99 /* Allow the builtin keyring to be added to the secondary */ in restrict_link_by_builtin_and_secondary_trusted()
114 * being vouched for by a key in either the built-in or the secondary system
122 /* If we have a secondary trusted keyring, then that contains a link in restrict_link_by_digsig_builtin_and_secondary()
128 /* Allow the builtin keyring to be added to the secondary */ in restrict_link_by_digsig_builtin_and_secondary()
136 * Allocate a struct key_restriction for the "builtin and secondary trust"
146 panic("Can't allocate secondary trusted keyring restriction\n"); in get_builtin_and_secondary_restriction()
157 * add_to_secondary_keyring - Add to secondary keyring.
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/openbmc/linux/sound/soc/qcom/qdsp6/
H A Dq6dsp-lpass-ports.c360 .stream_name = "Secondary MI2S Playback",
373 .stream_name = "Secondary MI2S Capture",
483 Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
484 Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
485 Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
486 Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
487 Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
488 Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
489 Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
490 Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
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/openbmc/linux/Documentation/admin-guide/blockdev/drbd/
H A Dpeer-states-8.dot2 Secondary -> Primary [ label = "recv state packet" ]
3 Primary -> Secondary [ label = "recv state packet" ]
5 Secondary -> Unknown [ label = "connection lost" ]
7 Unknown -> Secondary [ label = "connected" ]
/openbmc/linux/arch/arm64/include/asm/
H A Dsmp.h20 /* Fatal system error detected by secondary CPU, crash the system */
70 * Called from the secondary holding pen, this is the secondary CPU entry point.
75 * Initial data for bringing up a secondary CPU.
76 * @status - Result passed back from the secondary CPU to
122 * The calling secondary CPU has detected serious configuration mismatch,
133 * If a secondary CPU enters the kernel but fails to come online,
/openbmc/linux/Documentation/arch/sparc/oradax/
H A Ddax-hv-api.txt172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
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/openbmc/linux/arch/arm/mach-mvebu/
H A Dheadsmp.S3 * SMP support: Entry point for secondary CPUs
11 * This file implements the assembly entry point for secondary CPUs in
24 * Armada XP specific entry point for secondary CPUs.
25 * We add the CPU to the coherency fabric and then jump to secondary
/openbmc/webui-vue/docs/guide/components/buttons/
H A Dindex.md4 the `primary` and `secondary` buttons. Buttons, like all Boostrap-vue components
27 <b-button variant="secondary">Secondary</b-button>
50 <b-button disabled variant="secondary">Secondary</b-button>
/openbmc/u-boot/doc/
H A DREADME.arm6432 4. Spin-table is used to wake up secondary processors. One location
34 for secondary processors. It must be ensured that the location is
35 accessible and zero immediately after secondary processor
38 of secondary processors to it and send event to wakeup secondary
H A DREADME.mpc85xx-spin-table12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpamu.txt63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
/openbmc/linux/arch/arm/mach-omap2/
H A Domap-headsmp.S3 * Secondary CPU startup routine source file.
21 /* Physical address needed since MMU not enabled yet on secondary core */
36 * OMAP5 specific entry point for secondary CPU to jump from ROM
38 * secondary core is held until we're ready for it to initialise.
75 * OMAP4 specific entry point for secondary CPU to jump from ROM
77 * secondary core is held until we're ready for it to initialise.
/openbmc/qemu/tests/unit/
H A Dtest-replication.c28 /* secondary */
29 #define S_ID "secondary-id"
30 #define S_LOCAL_DISK_ID "secondary-local-disk-id"
151 /* Secondary */ in prepare_imgs()
165 /* Secondary */ in cleanup_imgs()
315 cmdline = g_strdup_printf("driver=replication,mode=secondary,top-id=%s," in start_secondary()
588 /* Secondary */ in main()
589 g_test_add_func("/replication/secondary/read", test_secondary_read); in main()
590 g_test_add_func("/replication/secondary/write", test_secondary_write); in main()
592 g_test_add_func("/replication/secondary/start", test_secondary_start); in main()
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/openbmc/openbmc/poky/meta/files/common-licenses/
H A DMPL-2.0-no-copyleft-exception13 1.5. "Incompatible With Secondary Licenses" means
17 …erms of version 1.1 or earlier of the License, but not also under the terms of a Secondary License.
35 …1.12. "Secondary License" means either the GNU General Public License, Version 2.0, the GNU Lesser…
65 …uent version of this License (see Section 10.2) or under the terms of a Secondary License (if perm…
89 …Secondary Licenses, and the Covered Software is not Incompatible With Secondary Licenses, this Lic…
131 10.4. Distributing Source Code Form that is Incompatible With Secondary Licenses
132 …If You choose to distribute Source Code Form that is Incompatible With Secondary Licenses under th…
142 Exhibit B - "Incompatible With Secondary Licenses" Notice
144 …This Source Code Form is "Incompatible With Secondary Licenses", as defined by the Mozilla Public …
/openbmc/linux/arch/arm/mach-versatile/
H A Dplatsmp.c45 * calibrations on the secondary CPU while the requesting CPU is using
72 * and the secondary one in versatile_boot_secondary()
77 * This is really belt and braces; we hold unintended secondary in versatile_boot_secondary()
85 * Send the secondary CPU a soft interrupt, thereby causing in versatile_boot_secondary()
101 * now the secondary core is starting up let it run its in versatile_boot_secondary()
/openbmc/linux/arch/arm/mach-spear/
H A Dplatsmp.c62 * and the secondary one in spear13xx_boot_secondary()
67 * The secondary processor is waiting to be released from in spear13xx_boot_secondary()
86 * now the secondary core is starting up let it run its in spear13xx_boot_secondary()
118 * Write the address of secondary startup into the system-wide location in spear13xx_smp_prepare_cpus()
120 * soft interrupt, and then the secondary CPU branches to this address. in spear13xx_smp_prepare_cpus()
/openbmc/linux/Documentation/arch/arm/samsung/
H A Dbootloader-interface.rst28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
46 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
60 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
72 0x0908 Non-zero Secondary CPU boot up indicator
/openbmc/linux/include/linux/
H A Dmmu_notifier.h70 * should tear down all secondary mmu mappings and freeze the
71 * secondary mmu. If this method isn't implemented you've to
73 * through the secondary mmu by the time the last thread with
80 * through the secondary mmu are terminated by the time the
95 * accesses to the page through the secondary MMUs and not
97 * Start-end is necessary in case the secondary MMU is mapping the page
108 * in the secondary pte, but it may omit flushing the secondary tlb.
117 * the secondary pte. This is used to know if the page is
119 * down the secondary mapping on the page.
172 * any secondary tlb before doing the final free on the
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-qds.dts110 mdio@0 { /* Slot #1 (secondary EMI) */
116 mdio@1 { /* Slot #2 (secondary EMI) */
122 mdio@2 { /* Slot #3 (secondary EMI) */
128 mdio@3 { /* Slot #4 (secondary EMI) */
134 mdio@4 { /* Slot #5 (secondary EMI) */
140 mdio@5 { /* Slot #6 (secondary EMI) */
146 mdio@6 { /* Slot #7 (secondary EMI) */
152 mdio@7 { /* Slot #8 (secondary EMI) */

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