1*e790a4ceSJonathan Corbet========================================================== 2*e790a4ceSJonathan CorbetInterface between kernel and boot loaders on Exynos boards 3*e790a4ceSJonathan Corbet========================================================== 4*e790a4ceSJonathan Corbet 5*e790a4ceSJonathan CorbetAuthor: Krzysztof Kozlowski 6*e790a4ceSJonathan Corbet 7*e790a4ceSJonathan CorbetDate : 6 June 2015 8*e790a4ceSJonathan Corbet 9*e790a4ceSJonathan CorbetThe document tries to describe currently used interface between Linux kernel 10*e790a4ceSJonathan Corbetand boot loaders on Samsung Exynos based boards. This is not a definition 11*e790a4ceSJonathan Corbetof interface but rather a description of existing state, a reference 12*e790a4ceSJonathan Corbetfor information purpose only. 13*e790a4ceSJonathan Corbet 14*e790a4ceSJonathan CorbetIn the document "boot loader" means any of following: U-boot, proprietary 15*e790a4ceSJonathan CorbetSBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before 16*e790a4ceSJonathan Corbetexecuting kernel. 17*e790a4ceSJonathan Corbet 18*e790a4ceSJonathan Corbet 19*e790a4ceSJonathan Corbet1. Non-Secure mode 20*e790a4ceSJonathan Corbet 21*e790a4ceSJonathan CorbetAddress: sysram_ns_base_addr 22*e790a4ceSJonathan Corbet 23*e790a4ceSJonathan Corbet============= ============================================ ================== 24*e790a4ceSJonathan CorbetOffset Value Purpose 25*e790a4ceSJonathan Corbet============= ============================================ ================== 26*e790a4ceSJonathan Corbet0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend 27*e790a4ceSJonathan Corbet0x0c 0x00000bad (Magic cookie) System suspend 28*e790a4ceSJonathan Corbet0x1c exynos4_secondary_startup Secondary CPU boot 29*e790a4ceSJonathan Corbet0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot 30*e790a4ceSJonathan Corbet0x20 0xfcba0d10 (Magic cookie) AFTR 31*e790a4ceSJonathan Corbet0x24 exynos_cpu_resume_ns AFTR 32*e790a4ceSJonathan Corbet0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR 33*e790a4ceSJonathan Corbet0x28 0x0 or last value during resume (Exynos542x) System suspend 34*e790a4ceSJonathan Corbet============= ============================================ ================== 35*e790a4ceSJonathan Corbet 36*e790a4ceSJonathan Corbet 37*e790a4ceSJonathan Corbet2. Secure mode 38*e790a4ceSJonathan Corbet 39*e790a4ceSJonathan CorbetAddress: sysram_base_addr 40*e790a4ceSJonathan Corbet 41*e790a4ceSJonathan Corbet============= ============================================ ================== 42*e790a4ceSJonathan CorbetOffset Value Purpose 43*e790a4ceSJonathan Corbet============= ============================================ ================== 44*e790a4ceSJonathan Corbet0x00 exynos4_secondary_startup Secondary CPU boot 45*e790a4ceSJonathan Corbet0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot 46*e790a4ceSJonathan Corbet4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot 47*e790a4ceSJonathan Corbet0x20 exynos_cpu_resume (Exynos4210 r1.0) AFTR 48*e790a4ceSJonathan Corbet0x24 0xfcba0d10 (Magic cookie, Exynos4210 r1.0) AFTR 49*e790a4ceSJonathan Corbet============= ============================================ ================== 50*e790a4ceSJonathan Corbet 51*e790a4ceSJonathan CorbetAddress: pmu_base_addr 52*e790a4ceSJonathan Corbet 53*e790a4ceSJonathan Corbet============= ============================================ ================== 54*e790a4ceSJonathan CorbetOffset Value Purpose 55*e790a4ceSJonathan Corbet============= ============================================ ================== 56*e790a4ceSJonathan Corbet0x0800 exynos_cpu_resume AFTR, suspend 57*e790a4ceSJonathan Corbet0x0800 mcpm_entry_point (Exynos542x with MCPM) AFTR, suspend 58*e790a4ceSJonathan Corbet0x0804 0xfcba0d10 (Magic cookie) AFTR 59*e790a4ceSJonathan Corbet0x0804 0x00000bad (Magic cookie) System suspend 60*e790a4ceSJonathan Corbet0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot 61*e790a4ceSJonathan Corbet0x0818 0xfcba0d10 (Magic cookie, Exynos4210 r1.1) AFTR 62*e790a4ceSJonathan Corbet0x081C exynos_cpu_resume (Exynos4210 r1.1) AFTR 63*e790a4ceSJonathan Corbet============= ============================================ ================== 64*e790a4ceSJonathan Corbet 65*e790a4ceSJonathan Corbet3. Other (regardless of secure/non-secure mode) 66*e790a4ceSJonathan Corbet 67*e790a4ceSJonathan CorbetAddress: pmu_base_addr 68*e790a4ceSJonathan Corbet 69*e790a4ceSJonathan Corbet============= =============================== =============================== 70*e790a4ceSJonathan CorbetOffset Value Purpose 71*e790a4ceSJonathan Corbet============= =============================== =============================== 72*e790a4ceSJonathan Corbet0x0908 Non-zero Secondary CPU boot up indicator 73*e790a4ceSJonathan Corbet on Exynos3250 and Exynos542x 74*e790a4ceSJonathan Corbet============= =============================== =============================== 75*e790a4ceSJonathan Corbet 76*e790a4ceSJonathan Corbet 77*e790a4ceSJonathan Corbet4. Glossary 78*e790a4ceSJonathan Corbet 79*e790a4ceSJonathan CorbetAFTR - ARM Off Top Running, a low power mode, Cortex cores and many other 80*e790a4ceSJonathan Corbetmodules are power gated, except the TOP modules 81*e790a4ceSJonathan CorbetMCPM - Multi-Cluster Power Management 82