| /openbmc/linux/drivers/net/dsa/sja1105/ |
| H A D | Kconfig | 3 tristate "NXP SJA1105 Ethernet switch family support"
11 This is the driver for the NXP SJA1105 (5-port) and SJA1110 (10-port)
27 bool "Support for the PTP clock on the NXP SJA1105 Ethernet switch"
32 the SJA1105 DSA driver.
35 bool "Support for the Time-Aware Scheduler on NXP SJA1105"
41 engine in the SJA1105 DSA driver, which is controlled using a
45 bool "Support for Virtual Links on NXP SJA1105"
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| H A D | Makefile | 2 obj-$(CONFIG_NET_DSA_SJA1105) += sja1105.o
4 sja1105-objs := \
16 sja1105-objs += sja1105_ptp.o
20 sja1105-objs += sja1105_tas.o
24 sja1105-objs += sja1105_vl.o
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| H A D | sja1105_ptp.c | 5 #include "sja1105.h"
19 * immediately after the CAS_MASTER SJA1105 switch has performed a CASSYNC
188 /* The switch returns partial timestamps (24 bits for SJA1105 E/T, which wrap
224 * SJA1105 E/T layout of the 4-byte SPI payload:
234 * SJA1105 P/Q/R/S layout of the 8-byte SPI payload:
892 .name = "SJA1105 PHC", in sja1105_ptp_clock_register()
907 /* Only used on SJA1105 */ in sja1105_ptp_clock_register()
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| H A D | sja1105_dynamic_config.h | 7 #include "sja1105.h"
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| H A D | sja1105_vl.h | 7 #include "sja1105.h"
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| H A D | sja1105_clocking.c | 6 #include "sja1105.h"
52 * SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
53 * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
486 * SJA1105, so just hardcode the frequency range to automatic, just as in sja1110_cfg_pad_mii_id_packing()
503 * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
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| H A D | sja1105_devlink.c | 5 #include "sja1105.h"
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| H A D | sja1105_mdio.c | 6 #include "sja1105.h"
383 bus->name = "SJA1105 PCS MDIO bus"; in sja1105_mdiobus_pcs_register()
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| H A D | sja1105_ptp.h | 78 /* Used only on SJA1105 to reconstruct partial timestamps */
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| H A D | sja1105_main.c | 24 #include "sja1105.h"
650 /* Nothing to do for SJA1105 */ in sja1110_init_pcp_remapping()
808 * switch generation. On SJA1105 we need to set an invalid port, while in sja1105_init_topology()
1264 /* Convert link speed from SJA1105 to ethtool encoding */
1413 /* The SJA1105 MAC programming model is through the static in sja1105_phylink_get_caps()
1455 * across switch resets, which are a common thing during normal SJA1105
3076 /* The programming model for the SJA1105 switch is "all-at-once" via static
3080 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3147 /* On SJA1105, VLAN filtering per se is always enabled in hardware. in sja1105_setup()
3306 dev_err(dev, "No DTS bindings for SJA1105 driver\n"); in sja1105_probe()
[all …]
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| H A D | sja1105_dynamic_config.c | 4 #include "sja1105.h"
79 * Only the TCAM-based FDB table on SJA1105 P/Q/R/S supports
273 /* VALIDENT is supposed to indicate "keep or not", but in SJA1105 E/T, in sja1105pqrs_common_l2_lookup_cmd_packing()
281 * SJA1105 P/Q/R/S keeps the same behavior w.r.t. VALIDENT, but there in sja1105pqrs_common_l2_lookup_cmd_packing()
1390 * the SJA1105 E/T FDB keys (vlanid, macaddr) as input. CRC polynomial
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| H A D | sja1105_spi.c | 8 #include "sja1105.h"
353 /* Put the SJA1105 in programming mode */ in sja1105_static_config_upload()
368 /* Check that SJA1105 responded well to the config upload */ in sja1105_static_config_upload()
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| H A D | sja1105.h | 10 #include <linux/dsa/sja1105.h>
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| /openbmc/linux/Documentation/networking/dsa/ |
| H A D | sja1105.rst | 2 NXP SJA1105 switch driver
8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
233 asking sja1105 to offload it. One (or more) redirect or trap actions must also
243 Receiver (sja1105)::
299 The SJA1105 switch family always performs VLAN processing. When configured as
326 This section references ``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml``
337 On the other hand, the SJA1105 is only binary configurable - when in the RMII
345 So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the
346 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
349 simply encodes the extra symbols received from the SJA1105-as-PHY onto the
[all …]
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| H A D | index.rst | 12 sja1105
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| /openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | nxp,sja1105.yaml | 4 $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
7 title: NXP SJA1105 Automotive Ethernet Switch Family
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
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| /openbmc/linux/include/linux/dsa/ |
| H A D | sja1105.h | 5 /* Included by drivers/net/dsa/sja1105/sja1105.h and net/dsa/tag_sja1105.c */
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| /openbmc/linux/net/dsa/ |
| H A D | Kconfig | 155 tristate "Tag driver for NXP SJA1105 switches"
159 NXP SJA1105 switch family. Both the native tagging protocol (which
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| H A D | tag_sja1105.c | 5 #include <linux/dsa/sja1105.h>
12 #define SJA1105_NAME "sja1105"
112 * Also SJA1105 E/T only populates bits 23:0 of the timestamp in sja1105_meta_unpack()
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| /openbmc/linux/drivers/net/dsa/ |
| H A D | Makefile | 27 obj-y += sja1105/
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| H A D | Kconfig | 86 source "drivers/net/dsa/sja1105/Kconfig"
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| /openbmc/linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a-tsn.dts | 41 sja1105: ethernet-switch@1 { label
50 /* SPI controller settings for SJA1105 timing requirements */
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| /openbmc/linux/drivers/net/pcs/ |
| H A D | pcs-xpcs-nxp.c | 67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp151a-prtt1c.dts | 20 clock_sja1105: clock-sja1105 {
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qp-prtwd3.dts | 47 clock_sja1105: clock-sja1105 {
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