Home
last modified time | relevance | path

Searched full:sgis (Results 1 – 25 of 30) sorted by relevance

12

/openbmc/linux/include/kvm/
H A Darm_vgic.h122 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
148 u8 source; /* GICv2 SGIs only */
149 u8 active_source; /* GICv2 SGIs only */
258 /* Wants SGIs without active state */
/openbmc/u-boot/arch/arm/lib/
H A Dgic_64.S106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
140 * Initialize SGIs and PPIs
144 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
/openbmc/qemu/hw/intc/
H A Darm_gicv3_dist.c100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_bitmap_reg()
123 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_set_bitmap_reg()
147 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_clear_bitmap_reg()
171 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_read_bitmap_reg()
454 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_readl()
536 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_readl()
662 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_writel()
749 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_writel()
H A Darm_gicv3.c181 * redistributor interrupts (SGIs and PPIs). in gicv3_redist_update_noirqset()
394 /* Raising SGIs via this function would be a bug in how the board in gicv3_set_irq()
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
180 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
599 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
1082 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
1084 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1143 * An access targeting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
1144 * those, while an access targeting Group1 SGIs can in vgic_v3_dispatch_sgi()
H A Dvgic.c95 /* SGIs and PPIs */ in vgic_get_irq()
612 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
788 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
820 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
H A Dvgic-init.c208 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
221 /* SGIs */ in kvm_vgic_vcpu_init()
H A Dvgic-mmio.c361 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
453 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
760 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,omap4-wugen-mpu20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
H A Darm,gic.yaml17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
H A Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/files/
H A D0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch6 OP-TEE requires SGIs to be handled at S-EL1. The
/openbmc/u-boot/arch/arm/include/asm/
H A Dgic.h71 /* ReDistributor Registers for SGIs and PPIs */
/openbmc/linux/drivers/irqchip/
H A Dirq-hip04.c122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
329 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
H A Dirq-gic-common.c112 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
H A Dirq-alpine-msi.c35 u32 num_spis; /* The number of SGIs for MSIs */
H A Dirq-gic.c300 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
368 * works because we don't nest SGIs... in gic_handle_irq()
1003 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
1010 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
H A Dirq-gic-v3.c664 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
954 pr_info("Enabling SGIs without active state\n"); in gic_dist_init()
1233 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
1288 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1398 /* Register all 8 non-secure SGIs */ in gic_smp_init()
/openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dvgic.c113 "doesn't allow injecting SGIs. There's no mask for it."); in _kvm_arm_irq_line()
H A Dgic_v3.c308 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
/openbmc/qemu/include/hw/intc/
H A Darm_gic_common.h29 /* First 32 are private to each CPU (SGIs and PPIs). */
H A Darm_gicv3_common.h62 * space for the PPIs and SGIs, those bits (the first 32) are never
/openbmc/linux/drivers/gpio/
H A Dgpio-xgene-sb.c195 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_irq.c543 * The kernel silently fails for invalid SPIs and SGIs (which in kvm_irq_set_level_info_check()
595 * either trying to inject SGIs when we configured the test to be in kvm_irq_write_ispendr_check()
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst273 SGIs and any interrupt with a higher ID than the number of interrupts

12