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/openbmc/u-boot/board/freescale/b4860qds/
H A Deth_b4860qds.c54 * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
64 debug("Initializing lane to slot: Serdes2 protocol: %x\n", in initialize_lane_to_slot()
140 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", in initialize_lane_to_slot()
171 printf("SERDES2 is not enabled\n"); in board_eth_init()
175 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); in board_eth_init()
296 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", in board_eth_init()
H A Db4860qds.c350 printf("SERDES2 is not enabled\n"); in configure_vsc3316_3308()
354 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); in configure_vsc3316_3308()
589 " SerDes2 Protocol.\n", serdes2_prtcl); in configure_vsc3316_3308()
764 printf("SerDes2, PLL:%d didnt lock\n", i); in check_serdes_pll_locks()
915 debug("SERDES2 is not enabled\n"); in config_serdes2_refclks()
919 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); in config_serdes2_refclks()
928 * For this SerDes2's Refclk1 need to be set to 100MHz in config_serdes2_refclks()
1042 /* SerDes2 refclks need to be set again, as default clks in board_early_init_r()
1044 * This function will set SerDes2's Refclk1 and refclk2 in board_early_init_r()
1045 * for SerDes2 protocols having PCIe in them in board_early_init_r()
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/openbmc/u-boot/board/freescale/ls2080aqds/
H A Deth.c533 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", in initialize_dpmac_to_slot()
555 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", in initialize_dpmac_to_slot()
571 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", in initialize_dpmac_to_slot()
586 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", in initialize_dpmac_to_slot()
613 goto serdes2; in ls2080a_handle_phy_interface_sgmii()
676 serdes2: in ls2080a_handle_phy_interface_sgmii()
729 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", in ls2080a_handle_phy_interface_sgmii()
/openbmc/u-boot/drivers/net/fm/
H A Dt4240.c153 /* check lane G on SerDes2 */ in fman_port_enet_if()
161 /* check lane C on SerDes2 */ in fman_port_enet_if()
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME21 - SERDES2 Connections, 4 lanes supporting:
/openbmc/u-boot/doc/
H A DREADME.b4860qds307 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
308 0x2a, 0xb2 (serdes1, serdes2)
323 0x18, 0x9e (serdes1, serdes2)
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
/openbmc/u-boot/board/freescale/t4rdb/
H A Deth.c117 puts("Invalid SerDes2 protocol for T4240RDB\n"); in board_eth_init()
H A Dt4240rdb.c44 printf(" SERDES1=100MHz SERDES2=156.25MHz\n" in checkboard()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dp5040_serdes.c13 * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
/openbmc/u-boot/board/freescale/t208xqds/
H A Dt208xqds.c273 /* SerDes2 is not enabled */ in brd_mux_lane_to_slot()
322 printf("WARNING: unsupported for SerDes2 Protocol %d\n", in brd_mux_lane_to_slot()
/openbmc/linux/include/linux/fsl/
H A Dguts.h130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
/openbmc/u-boot/board/freescale/lx2160a/
H A DREADME25 Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
153 SERDES2 |CARDS
H A Dlx2160a.c277 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); in checkboard()
H A Deth_lx2160aqds.c528 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n", in board_eth_init()
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c57 " 2 for SerDes2.\n"); in set_serdes_refclk()
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-common-proc-board.dts895 &serdes2 {
896 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
H A Dk3-j721e-beagleboneai64.dts668 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
726 &serdes2 {
H A Dk3-j721e-sk.dts750 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
808 &serdes2 {
H A Dk3-j721e-main.dtsi53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
735 serdes2: serdes@5020000 { label
/openbmc/u-boot/board/freescale/t4qds/
H A Deth.c772 puts("Invalid SerDes2 protocol for T4240QDS\n"); in board_eth_init()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h1121 uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
1122 uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */