/openbmc/linux/arch/riscv/net/ |
H A D | bpf_jit.h | 229 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument 232 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_r_insn() 236 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument 238 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn() 242 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_s_insn() argument 246 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_s_insn() 250 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_b_insn() argument 255 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn() 274 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, in rv_amo_insn() argument 279 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn() [all …]
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/openbmc/qemu/target/riscv/ |
H A D | fpu_helper.c | 121 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h() argument 124 float16 frs1 = check_nanbox_h(env, rs1); in do_fmadd_h() 131 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s() argument 134 float32 frs1 = check_nanbox_s(env, rs1); in do_fmadd_s() 218 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fadd_s() argument 220 float32 frs1 = check_nanbox_s(env, rs1); in helper_fadd_s() 225 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fsub_s() argument 227 float32 frs1 = check_nanbox_s(env, rs1); in helper_fsub_s() 232 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fmul_s() argument 234 float32 frs1 = check_nanbox_s(env, rs1); in helper_fmul_s() [all …]
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H A D | crypto_helper.c | 31 target_ulong rs1, target_ulong rs2, in aes32_operation() argument 52 res = rs1 ^ mixed; in aes32_operation() 57 target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, in HELPER() 60 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER() 63 target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, in HELPER() 66 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER() 69 target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2, in HELPER() 72 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER() 75 target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2, in HELPER() 78 return aes32_operation(shamt, rs1, rs2, false, false); in HELPER() [all …]
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H A D | insn16.decode | 56 &r rd rs1 rs2 !extern 57 &i imm rs1 rd !extern 58 &s imm rs1 rs2 !extern 60 &b imm rs2 rs1 !extern 62 &shift shamt rs1 rd !extern 63 &r2 rd rs1 !extern 64 &r2_s rs1 rs2 !extern 70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd 71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd 72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 [all …]
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H A D | bitmanip_helper.c | 27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER() 33 result ^= (rs1 << i); in HELPER() 40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER() 46 result ^= (rs1 >> (TARGET_LONG_BITS - i - 1)); in HELPER() 58 target_ulong HELPER(brev8)(target_ulong rs1) in HELPER() 60 target_ulong x = rs1; in HELPER() 84 target_ulong HELPER(unzip)(target_ulong rs1) in HELPER() 86 target_ulong x = rs1; in HELPER() 95 target_ulong HELPER(zip)(target_ulong rs1) in HELPER() 97 target_ulong x = rs1; in HELPER() [all …]
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H A D | xthead.decode | 16 %rs1 15:5 26 &r rd rs1 rs2 !extern 27 &r2 rd rs1 !extern 28 &shift shamt rs1 rd !extern 29 &th_bfext msb lsb rs1 rd 31 &th_memidx rd rs1 rs2 imm2 32 &th_meminc rd rs1 imm5 imm2 35 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd [all …]
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/openbmc/linux/arch/riscv/include/asm/ |
H A D | insn-def.h | 25 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 26 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 29 .macro insn_i, opcode, func3, rd, rs1, simm12 30 .insn i \opcode, \func3, \rd, \rs1, \simm12 37 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 42 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \ 46 .macro insn_i, opcode, func3, rd, rs1, simm12 50 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \ 63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument 64 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" [all …]
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H A D | errata_list.h | 108 * dcache.ipa rs1 (invalidate, physical address) 110 * 0000001 01010 rs1 000 00000 0001011 111 * dache.iva rs1 (invalida, virtual address) 112 * 0000001 00110 rs1 000 00000 0001011 114 * dcache.cpa rs1 (clean, physical address) 116 * 0000001 01001 rs1 000 00000 0001011 117 * dcache.cva rs1 (clean, virtual address) 118 * 0000001 00101 rs1 000 00000 0001011 120 * dcache.cipa rs1 (clean then invalidate, physical address) 122 * 0000001 01011 rs1 000 00000 0001011 [all …]
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvd.c.inc | 65 addr = get_address(ctx, a->rs1, a->imm); 89 addr = get_address(ctx, a->rs1, a->imm); 110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); 113 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); 128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); 131 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); 146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); 149 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); 164 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); 167 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); [all …]
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H A D | trans_rvzfh.c.inc | 52 t0 = get_gpr(ctx, a->rs1, EXT_NONE); 75 t0 = get_gpr(ctx, a->rs1, EXT_NONE); 93 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 110 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 127 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 144 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 161 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 177 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 193 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 209 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); [all …]
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H A D | trans_rvf.c.inc | 56 addr = get_address(ctx, a->rs1, a->imm); 78 addr = get_address(ctx, a->rs1, a->imm); 101 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 118 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 135 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 152 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 169 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 185 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 201 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 217 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); [all …]
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H A D | trans_xthead.c.inc | 87 * If !zext_offs, then the address is rs1 + (rs2 << imm2). 88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). 90 static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, 103 return get_address_indexed(ctx, rs1, offs); 110 * alternative encoding: while sh[123] applies the shift to rs1, 162 TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO); 187 TCGv src1 = get_gpr(ctx, a->rs1, ext); 314 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */ 332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */ [all …]
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H A D | trans_rvzfa.c.inc | 74 tcg_gen_movi_i64(dest, fli_s_table[a->rs1]); 123 tcg_gen_movi_i64(dest, fli_d_table[a->rs1]); 173 tcg_gen_movi_i64(dest, fli_h_table[a->rs1]); 187 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 204 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 221 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); 238 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); 255 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 272 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); 289 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); [all …]
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H A D | trans_rvi.c.inc | 102 tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm); 123 * return from functions (i.e. rs1 == xRA || rs1 == xT0) are not 125 * branch are not tracked. rs1 == xT2 is a sw guarded branch. 127 if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { 219 TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN); 224 TCGv src1h = get_gprh(ctx, a->rs1); 287 TCGv addr = get_address(ctx, a->rs1, a->imm); 297 TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE); 394 TCGv addr = get_address(ctx, a->rs1, a->imm); 407 TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE); [all …]
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/openbmc/qemu/tests/tcg/tricore/asm/ |
H A D | macros.h | 102 #define TEST_D_D(insn, num, result, rs1) \ argument 104 LI(DREG_RS1, rs1); \ 108 #define TEST_D_D_PSW(insn, num, result, psw, rs1) \ argument 110 LI(DREG_RS1, rs1); \ 115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ argument 117 LI(DREG_RS1, rs1); \ 124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument 126 LI(DREG_RS1, rs1); \ 132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument 134 LI(DREG_RS1, rs1); \ [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | visemul.c | 136 #define RS1(INSN) (((INSN) >> 14) & 0x1f) macro 140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument 143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows() 296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local 299 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in edge() 300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge() 304 rs1 = rs1 & 0xffffffff; in edge() 311 left = edge8_tab[rs1 & 0x7].left; in edge() 316 left = edge8_tab_l[rs1 & 0x7].left; in edge() 322 left = edge16_tab[(rs1 >> 1) & 0x3].left; in edge() [all …]
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H A D | unaligned_32.c | 72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument 75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows() 139 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local 144 maybe_flush_windows(rs1, 0, rd); in compute_effective_address() 145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address() 147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address() 148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address() 155 unsigned int rs1 = (insn >> 14) & 0x1f; in safe_compute_effective_address() local 160 maybe_flush_windows(rs1, 0, rd); in safe_compute_effective_address() 161 return (safe_fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in safe_compute_effective_address() [all …]
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/openbmc/linux/arch/sparc/crypto/ |
H A D | opcodes.h | 11 #define RS1(x) (FPD_ENCODE(x) << 14) macro 19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c)); 31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 35 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 37 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 39 .word (F3F(2, 0x19, 4)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 41 .word (F3F(2, 0x19, 5)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 43 .word (F3F(2, 0x19, 6)|RS1(a)|RS2(b)|RS3(c)|RD(d)); 45 .word (F3F(2, 0x19, 7)|RS1(a)|RS2(b)|RS3(c)|RD(d)); [all …]
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/openbmc/linux/arch/riscv/kernel/probes/ |
H A D | simulate-insn.c | 65 * offset[11:0] | rs1 | 010 | rd | opcode in simulate_jalr() 144 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode | in simulate_branch() 146 * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ in simulate_branch() 147 * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE in simulate_branch() 148 * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT in simulate_branch() 149 * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE in simulate_branch() 150 * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU in simulate_branch() 151 * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU in simulate_branch() 221 * | funct4 | rs1 | rs2 | op | in simulate_c_jr_jalr() 227 u32 rs1 = (opcode >> 7) & 0x1f; in simulate_c_jr_jalr() local [all …]
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/openbmc/qemu/tests/tcg/riscv64/ |
H A D | test-aes.c | 10 /* aes64es rd, rs1, rs2 = 0011001 rs2 rs1 000 rd 0110011 */ in test_SB_SR() 28 /* aesesm rd, rs1, rs2 = 0011011 rs2 rs1 000 rd 0110011 */ in test_SB_SR_MC_AK() 43 /* aes64ds rd, rs1, rs2 = 0011101 rs2 rs1 000 rd 0110011 */ in test_ISB_ISR() 55 /* aes64im rd, rs1 = 0011000 00000 rs1 001 rd 0010011 */ in test_IMC() 73 /* aes64dsm rd, rs1, rs2 = 0011111 rs2 rs1 000 rd 0110011 */ in test_ISB_ISR_IMC_AK()
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/openbmc/u-boot/post/lib_powerpc/ |
H A D | cpu_asm.h | 142 #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ argument 144 ((rs1) << 16) + \ 150 #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ argument 151 ((rs1) << 21) + \ 154 #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ argument 156 ((rs1) << 16) + \ 162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument 164 ((rs1) << 21) + \ 202 #define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) argument 204 #define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) argument
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/openbmc/qemu/target/sparc/ |
H A D | insns.decode | 17 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 38 &r_r_ri rd rs1 rs2_or_imm imm:bool 39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri 42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool 43 @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc 44 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 45 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1 47 &r_r_r rd rs1 rs2 48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r [all …]
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/openbmc/linux/arch/sparc/net/ |
H A D | bpf_jit_comp_32.c | 26 #define RS1(X) ((X) << 14) macro 71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) 113 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \ 118 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \ 123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \ 140 *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \ 161 _insn |= RS1(r_A) | RD(r_A); \ 175 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \ 184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \ 190 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \ [all …]
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H A D | bpf_jit_comp_64.c | 55 #define RS1(X) ((X) << 14) macro 139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) 263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); in emit_reg_move() 284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); in emit_set_const_sext() 290 emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx); in emit_alu() 295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); in emit_alu3() 304 insn |= RS1(dst) | RD(dst); in emit_alu_K() 323 insn |= RS1(src) | RD(dst); in emit_alu3_K() 340 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm32() 350 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm() [all …]
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/openbmc/qemu/disas/ |
H A D | sparc.c | 116 1 rs1 register. 132 M alternate space register (asr) in rs1 156 r Single register that is both rs1 and rd. 164 U sparclet coprocessor registers in rs1 position 175 ? Privileged Register in rs1 (v9) 180 / Ancillary state register in rs1 (v9a) 200 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ macro 209 #define RS1_G0 RS1 (~0) 364 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ 368 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ [all …]
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