Searched full:ref_sel (Results 1 – 9 of 9) sorted by relevance
232 u32 ref_sel; member687 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | in ad4130_write_slot_setup()977 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()978 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()1097 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()1098 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()1130 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()1131 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()1407 enum ad4130_ref_sel ref_sel) in ad4130_get_ref_voltage() argument1409 switch (ref_sel) { in ad4130_get_ref_voltage()[all …]
65 that clock signal is always available, its rate is specified by REF_SEL75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
144 u8 ref_sel; member
206 See the description of bitfield REF_SEL in the reference manual
52 PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
271 ts->stmpe->ref_sel = val; in stmpe_ts_get_platform_info()
410 u8 refsel; /* REF_SEL field of register MDREF */
479 * REF_SEL pins. in set_usb3503_ref_clk()
552 STMPE_REF_SEL(stmpe->ref_sel); in stmpe811_adc_common_init()1396 stmpe->ref_sel = val; in stmpe_probe()