/openbmc/linux/drivers/input/serio/ |
H A D | hil_mlc.c | 2 * HIL MLC state machine and serio interface driver 37 * few bits of logic in addition to raw access to the HIL MLC, 44 * each time it runs, checking each MLC's progress at the current 45 * node in the state machine, and moving the MLC to subsequent nodes 66 MODULE_DESCRIPTION("HIL MLC serio"); 72 #define PREFIX "HIL MLC: " 87 static void hil_mlc_clear_di_map(hil_mlc *mlc, int val) in hil_mlc_clear_di_map() argument 92 mlc->di_map[j] = -1; in hil_mlc_clear_di_map() 95 static void hil_mlc_clear_di_scratch(hil_mlc *mlc) in hil_mlc_clear_di_scratch() argument 97 memset(&mlc->di_scratch, 0, sizeof(mlc->di_scratch)); in hil_mlc_clear_di_scratch() [all …]
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H A D | hp_sdc_mlc.c | 2 * Access to HP-HIL MLC through HP System Device Controller. 45 #define PREFIX "HP SDC MLC: " 50 MODULE_DESCRIPTION("Glue for onboard HIL MLC in HP-PARISC machines"); 65 hil_mlc *mlc = &hp_sdc_mlc; in hp_sdc_mlc_isr() local 67 write_lock(&mlc->lock); in hp_sdc_mlc_isr() 68 if (mlc->icount < 0) { in hp_sdc_mlc_isr() 70 up(&mlc->isem); in hp_sdc_mlc_isr() 73 idx = 15 - mlc->icount; in hp_sdc_mlc_isr() 75 mlc->ipacket[idx] |= data | HIL_ERR_INT; in hp_sdc_mlc_isr() 76 mlc->icount--; in hp_sdc_mlc_isr() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mtd/ |
H A D | lpc32xx-mlc.txt | 1 NXP LPC32xx SoC NAND MLC controller 4 - compatible: "nxp,lpc3220-mlc" 10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in 26 mlc: flash@200a8000 { 27 compatible = "nxp,lpc3220-mlc";
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/openbmc/linux/include/linux/ |
H A D | hil_mlc.h | 91 typedef int (hilse_func) (hil_mlc *mlc, int arg); 105 typedef int (hil_mlc_cts) (hil_mlc *mlc); 106 typedef int (hil_mlc_out) (hil_mlc *mlc); 107 typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout); 117 hil_mlc *mlc; member 130 void *priv; /* Data specific to a particular type of MLC */ 167 int hil_mlc_register(hil_mlc *mlc); 168 int hil_mlc_unregister(hil_mlc *mlc);
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H A D | hp_sdc.h | 102 #define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */ 103 #define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */ 144 #define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */ 148 #define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */ 158 #define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */ 246 HIL MLC R0,R1 i8042 HIL watchdog */ 248 /* Values used to (de)mangle input/output to/from the HIL MLC */ 250 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */ 251 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */ 255 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */ [all …]
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H A D | hil.h | 57 * implementing a software MLC to run HIL devices on a non-parisc machine. 101 /* The HIL MLC also has several error/status/control bits. We extend the 102 * "packet" to include these when direct access to the MLC is available, 105 * This way the device driver knows that the underlying MLC driver 109 HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
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/openbmc/linux/arch/arm/mach-lpc32xx/ |
H A D | phy3250.c | 27 .bus_id = "nand-mlc", 28 .min_signal = 12, /* MLC NAND Flash */ 67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
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/openbmc/linux/drivers/mtd/nand/raw/ |
H A D | lpc32xx_mlc.c | 3 * Driver for NAND MLC Controller in LPC32xx 38 * MLC NAND controller register offsets 235 /* Reset MLC controller */ in lpc32xx_nand_setup() 239 /* Get base clock for MLC block */ in lpc32xx_nand_setup() 248 /* Configure MLC Controller: Large Block, 5 Byte Address */ in lpc32xx_nand_setup() 540 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ in lpc32xx_write_page_lowlevel() 554 /* Read whole page - necessary with MLC controller! */ in lpc32xx_read_oob() 562 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ in lpc32xx_write_oob() 566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */ 585 "nand-mlc"); in lpc32xx_dma_setup() [all …]
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H A D | Kconfig | 178 tristate "NXP LPC32xx MLC NAND controller" 182 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND 187 by the MLC NAND controller.
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/openbmc/linux/include/linux/mtd/ |
H A D | lpc32xx_mlc.h | 3 * Platform data for LPC32xx SoC MLC NAND controller
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | hi6421.txt | 24 // supply for MLC NAND/ eMMC
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/openbmc/linux/drivers/video/fbdev/ |
H A D | imsttfb.c | 312 __u8 mlc[3]; /* Memory Loop Config 0x39 */ member 586 __u8 mlc, lckl_p; in set_imstt_regvals_tvp() local 594 mlc = init->mlc[0]; in set_imstt_regvals_tvp() 601 mlc = init->mlc[1]; in set_imstt_regvals_tvp() 608 mlc = init->mlc[2]; in set_imstt_regvals_tvp() 615 mlc = init->mlc[2]; in set_imstt_regvals_tvp() 645 par->cmap_regs[TVPIDATA] = mlc; eieio(); in set_imstt_regvals_tvp()
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/openbmc/u-boot/drivers/mtd/nand/raw/ |
H A D | lpc32xx_nand_mlc.c | 3 * LPC32xx MLC NAND flash controller driver 10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC 31 * MLC NAND controller registers. 79 * There is a single instance of the NAND MLC controller 131 /* Make sure MLC interrupts are disabled */ in lpc32xx_nand_init()
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc32xx.dtsi | 63 * Enable either SLC or MLC 72 mlc: flash@200a8000 { label 73 compatible = "nxp,lpc3220-mlc";
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/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/ |
H A D | partition.yaml | 51 on a partition attached to an MLC NAND thus making this partition
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
H A D | cpu.h | 15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
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/openbmc/u-boot/doc/ |
H A D | README.atmel_pmecc | 7 can be used to support both SLC and MLC NAND Flash devices. It supports to
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/hplip/hplip/ |
H A D | fix-libusb-paths.patch | 10 @@ -107,12 +107,11 @@ libhpmud_la_SOURCES = io/hpmud/hpmud.c io/hpmud/mlc.c io/hpmud/model.c io/hpm…
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/ |
H A D | fsl,ifc.yaml | 16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
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/openbmc/u-boot/drivers/mtd/ubi/ |
H A D | Kconfig | 37 However, in case of MLC NAND flashes which typically have eraseblock
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/openbmc/linux/include/uapi/mtd/ |
H A D | mtd-abi.h | 148 #define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */ 154 #define MTD_SLC_ON_MLC_EMULATION 0x4000 /* Emulate SLC behavior on MLC NANDs */
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/openbmc/u-boot/board/work-microwave/work_92105/ |
H A D | README | 5 - 1 GB SLC NAND, managed through MLC controller.
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
H A D | pipeline.json | 396 …MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand l… 420 …MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ en…
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/openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/ |
H A D | pipeline.json | 388 …MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand l… 412 …MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ en…
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/openbmc/linux/drivers/mtd/ubi/ |
H A D | Kconfig | 27 However, in case of MLC NAND flashes which typically have eraseblock
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