1*e861cfbeSVladimir Zapolskiy // SPDX-License-Identifier: GPL-2.0+
219d95e1aSKevin Wells /*
3f5c42271SRoland Stigge * Platform support for LPC32xx SoC
419d95e1aSKevin Wells *
519d95e1aSKevin Wells * Author: Kevin Wells <kevin.wells@nxp.com>
619d95e1aSKevin Wells *
7f5c42271SRoland Stigge * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
819d95e1aSKevin Wells * Copyright (C) 2010 NXP Semiconductors
919d95e1aSKevin Wells */
1019d95e1aSKevin Wells
11291dd71fSRoland Stigge #include <linux/amba/pl08x.h>
125b941238SRoland Stigge #include <linux/mtd/lpc32xx_mlc.h>
13a1e65c28SVladimir Zapolskiy #include <linux/mtd/lpc32xx_slc.h>
14a1e65c28SVladimir Zapolskiy #include <linux/of_platform.h>
1519d95e1aSKevin Wells
1619d95e1aSKevin Wells #include <asm/mach/arch.h>
1719d95e1aSKevin Wells #include "common.h"
1819d95e1aSKevin Wells
19d807af47SRoland Stigge static struct pl08x_channel_data pl08x_slave_channels[] = {
20d807af47SRoland Stigge {
21d807af47SRoland Stigge .bus_id = "nand-slc",
22d807af47SRoland Stigge .min_signal = 1, /* SLC NAND Flash */
23d807af47SRoland Stigge .max_signal = 1,
24d807af47SRoland Stigge .periph_buses = PL08X_AHB1,
25d807af47SRoland Stigge },
26d807af47SRoland Stigge {
27d807af47SRoland Stigge .bus_id = "nand-mlc",
28d807af47SRoland Stigge .min_signal = 12, /* MLC NAND Flash */
29d807af47SRoland Stigge .max_signal = 12,
30d807af47SRoland Stigge .periph_buses = PL08X_AHB1,
31d807af47SRoland Stigge },
32d807af47SRoland Stigge };
33d807af47SRoland Stigge
pl08x_get_signal(const struct pl08x_channel_data * cd)348ba85f8bSRoland Stigge static int pl08x_get_signal(const struct pl08x_channel_data *cd)
35d807af47SRoland Stigge {
368ba85f8bSRoland Stigge return cd->min_signal;
37d807af47SRoland Stigge }
38d807af47SRoland Stigge
pl08x_put_signal(const struct pl08x_channel_data * cd,int ch)398ba85f8bSRoland Stigge static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
40d807af47SRoland Stigge {
41d807af47SRoland Stigge }
42d807af47SRoland Stigge
43f5c42271SRoland Stigge static struct pl08x_platform_data pl08x_pd = {
444166a56aSLinus Walleij /* Some reasonable memcpy defaults */
454166a56aSLinus Walleij .memcpy_burst_size = PL08X_BURST_SZ_256,
464166a56aSLinus Walleij .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
47d807af47SRoland Stigge .slave_channels = &pl08x_slave_channels[0],
48d807af47SRoland Stigge .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
49d7cabeedSMark Brown .get_xfer_signal = pl08x_get_signal,
50d7cabeedSMark Brown .put_xfer_signal = pl08x_put_signal,
51d807af47SRoland Stigge .lli_buses = PL08X_AHB1,
52d807af47SRoland Stigge .mem_buses = PL08X_AHB1,
5319d95e1aSKevin Wells };
5419d95e1aSKevin Wells
555b941238SRoland Stigge static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
565b941238SRoland Stigge .dma_filter = pl08x_filter_id,
575b941238SRoland Stigge };
585b941238SRoland Stigge
595b941238SRoland Stigge static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
605b941238SRoland Stigge .dma_filter = pl08x_filter_id,
615b941238SRoland Stigge };
625b941238SRoland Stigge
6371d42e9cSVladimir Zapolskiy static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
64f5c42271SRoland Stigge OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
655b941238SRoland Stigge OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
665b941238SRoland Stigge &lpc32xx_slc_data),
675b941238SRoland Stigge OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
685b941238SRoland Stigge &lpc32xx_mlc_data),
69f5c42271SRoland Stigge { }
7019d95e1aSKevin Wells };
7119d95e1aSKevin Wells
lpc3250_machine_init(void)72f5c42271SRoland Stigge static void __init lpc3250_machine_init(void)
7319d95e1aSKevin Wells {
7419d95e1aSKevin Wells lpc32xx_serial_init();
7519d95e1aSKevin Wells
76435ebcbcSKefeng Wang of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
7719d95e1aSKevin Wells }
7819d95e1aSKevin Wells
7919c233b7SNicolas Pitre static const char *const lpc32xx_dt_compat[] __initconst = {
80f5c42271SRoland Stigge "nxp,lpc3220",
81f5c42271SRoland Stigge "nxp,lpc3230",
82f5c42271SRoland Stigge "nxp,lpc3240",
83f5c42271SRoland Stigge "nxp,lpc3250",
84f5c42271SRoland Stigge NULL
85f5c42271SRoland Stigge };
86f5c42271SRoland Stigge
87f5c42271SRoland Stigge DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
88bdec5dddSNicolas Pitre .atag_offset = 0x100,
8919d95e1aSKevin Wells .map_io = lpc32xx_map_io,
90f5c42271SRoland Stigge .init_machine = lpc3250_machine_init,
91f5c42271SRoland Stigge .dt_compat = lpc32xx_dt_compat,
9219d95e1aSKevin Wells MACHINE_END
93