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/openbmc/linux/drivers/video/fbdev/omap/
H A Dlcdc.c28 #include "lcdc.h"
31 #define MODULE_NAME "lcdc"
69 } lcdc; variable
73 lcdc.irq_mask |= mask; in enable_irqs()
78 lcdc.irq_mask &= ~mask; in disable_irqs()
109 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */ in enable_controller()
131 init_completion(&lcdc.last_frame_complete); in disable_controller()
133 if (!wait_for_completion_timeout(&lcdc.last_frame_complete, in disable_controller()
135 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n"); in disable_controller()
146 dev_err(lcdc.fbdev->dev, in reset_controller()
[all …]
/openbmc/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c26 #define IMX21LCDC_LSSAR 0x0000 /* LCDC Screen Start Address Register */
27 #define IMX21LCDC_LSR 0x0004 /* LCDC Size Register */
28 #define IMX21LCDC_LVPWR 0x0008 /* LCDC Virtual Page Width Register */
29 #define IMX21LCDC_LCPR 0x000C /* LCDC Cursor Position Register */
30 #define IMX21LCDC_LCWHB 0x0010 /* LCDC Cursor Width Height and Blink Register*/
31 #define IMX21LCDC_LCCMR 0x0014 /* LCDC Color Cursor Mapping Register */
32 #define IMX21LCDC_LPCR 0x0018 /* LCDC Panel Configuration Register */
33 #define IMX21LCDC_LHCR 0x001C /* LCDC Horizontal Configuration Register */
34 #define IMX21LCDC_LVCR 0x0020 /* LCDC Vertical Configuration Register */
35 #define IMX21LCDC_LPOR 0x0024 /* LCDC Panning Offset Register */
[all …]
/openbmc/u-boot/drivers/video/sunxi/
H A Dlcdc.c13 #include <asm/arch/lcdc.h>
30 void lcdc_init(struct sunxi_lcdc_reg * const lcdc) in lcdc_init() argument
32 /* Init lcdc */ in lcdc_init()
33 writel(0, &lcdc->ctrl); /* Disable tcon */ in lcdc_init()
34 writel(0, &lcdc->int0); /* Disable all interrupts */ in lcdc_init()
37 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); in lcdc_init()
40 writel(0xffffffff, &lcdc->tcon0_io_tristate); in lcdc_init()
41 writel(0xffffffff, &lcdc->tcon1_io_tristate); in lcdc_init()
44 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth) in lcdc_enable() argument
46 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
[all …]
H A Dsunxi_lcd.c16 #include <asm/arch/lcdc.h>
42 struct sunxi_lcdc_reg * const lcdc = in sunxi_lcd_enable() local
53 lcdc_init(lcdc); in sunxi_lcd_enable()
57 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false, in sunxi_lcd_enable()
59 lcdc_enable(lcdc, priv->panel_bpp); in sunxi_lcd_enable()
H A DMakefile6 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o
7 obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_…
H A Dsunxi_dw_hdmi.c15 #include <asm/arch/lcdc.h>
258 struct sunxi_lcdc_reg *lcdc; in sunxi_dw_hdmi_lcdc_init() local
261 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; in sunxi_dw_hdmi_lcdc_init()
271 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE; in sunxi_dw_hdmi_lcdc_init()
282 lcdc_init(lcdc); in sunxi_dw_hdmi_lcdc_init()
283 lcdc_tcon1_mode_set(lcdc, edid, false, false); in sunxi_dw_hdmi_lcdc_init()
284 lcdc_enable(lcdc, bpp); in sunxi_dw_hdmi_lcdc_init()
H A Dsunxi_display.c15 #include <asm/arch/lcdc.h>
525 struct sunxi_lcdc_reg * const lcdc = in sunxi_lcdc_init() local
545 lcdc_init(lcdc); in sunxi_lcdc_init()
647 struct sunxi_lcdc_reg * const lcdc = local
674 lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
683 struct sunxi_lcdc_reg * const lcdc = local
690 lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
928 struct sunxi_lcdc_reg * const lcdc = local
943 lcdc_enable(lcdc, sunxi_display.depth);
973 lcdc_enable(lcdc, sunxi_display.depth);
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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Datmel,lcdc.txt1 Atmel LCDC Framebuffer
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
30 compatible = "atmel,at91sam9g45-lcdc";
44 compatible = "atmel,at91sam9263-lcdc";
49 Atmel LCDC Display
H A Dmarvell,pxa2xx-lcdc.txt6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
25 compatible = "marvell,pxa2xx-lcdc";
/openbmc/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx-lcdc.yaml4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
25 - const: fsl,imx25-lcdc
26 - const: fsl,imx21-lcdc
66 LCDC Sharp Configuration Register value.
74 - fsl,imx1-lcdc
75 - fsl,imx21-lcdc
104 lcdc@53fbc000 {
105 compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc";
/openbmc/linux/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.c2 * SuperH Mobile LCDC Framebuffer
147 * struct sh_mobile_lcdc_overlay - LCDC display overlay
149 * @channel: LCDC channel this overlay belongs to
217 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
290 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_write_chan()
292 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan()
299 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan_mirror()
306 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_read_chan()
312 iowrite32(data, ovl->channel->lcdc->base + reg); in lcdc_write_overlay()
313 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); in lcdc_write_overlay()
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H A Dsh_mobile_lcdcfb.h44 struct sh_mobile_lcdc_chan *lcdc; member
49 * struct sh_mobile_lcdc_chan - LCDC display channel
57 struct sh_mobile_lcdc_priv *lcdc; member
H A Dsh7760fb.c3 * SH7760/SH7763 LCDC Framebuffer driver.
69 /* en/disable the LCDC */
216 /* calculate LCDC reg vals from display parameters */ in sh7760fb_set_par()
248 /* shut down LCDC before changing display parameters */ in sh7760fb_set_par()
418 "unusable for the LCDC\n", (unsigned long)par->fbdma); in sh7760fb_alloc_mem()
476 "sh7760-lcdc", &par->vsync); in sh7760fb_probe()
511 strcpy(info->fix.id, "sh7760-lcdc"); in sh7760fb_probe()
574 .name = "sh7760-lcdc",
H A Datmel_lcdfb.c267 /* Wait for the LCDC core to become idle */ in atmel_lcdfb_stop_nowait()
577 /* Now, the LCDC core... */ in atmel_lcdfb_set_par()
878 { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
879 { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
880 { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
881 { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
882 { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
883 { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
1068 /* Enable LCDC Clocks */ in atmel_lcdfb_probe()
1132 /* LCDC registers */ in atmel_lcdfb_probe()
[all …]
/openbmc/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_regs.h10 /* LCDC register definitions, based on da8xx-fb */
16 /* LCDC Status Register */
24 /* LCDC DMA Control Register */
39 /* LCDC Control Register */
44 /* LCDC Raster Control Register */
71 /* LCDC Raster Timing 2 Register */
83 /* LCDC Block */
H A DKconfig3 tristate "DRM Support for TI LCDC Display Controller"
12 Choose this option if you have an TI SoC with LCDC display
/openbmc/linux/arch/sh/include/asm/
H A Dsh7760fb.h3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
96 /* Display types supported by the LCDC */
120 /* LCDC Pixclock sources */
128 /* LCDC pixclock input divider. Set to 1 at a minimum! */
182 /* set this member to 1 if you wish to use the LCDC's hardware
192 * more than the LCDC in terms of blanking (e.g. disable clock
/openbmc/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dtilcdc.txt8 - reg: base address and size of the LCDC device
11 - ti,hwmods: Name of the hwmod associated to the LCDC
21 This property deals with the LCDC revision 2 (found on AM335x)
41 tfp410 DVI encoder or lcd panel to lcdc
58 ti,hwmods = "lcdc";
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm8660.c752 MSM_PIN_FUNCTION(lcdc),
773 PINGROUP(0, lcdc, dsub, _, _, _, _, _),
774 PINGROUP(1, lcdc, dsub, _, _, _, _, _),
775 PINGROUP(2, lcdc, dsub, _, _, _, _, _),
776 PINGROUP(3, lcdc, dsub, _, _, _, _, _),
777 PINGROUP(4, lcdc, dsub, _, _, _, _, _),
778 PINGROUP(5, lcdc, dsub, _, _, _, _, _),
779 PINGROUP(6, lcdc, dsub, _, _, _, _, _),
780 PINGROUP(7, lcdc, dsub, _, _, _, _, _),
781 PINGROUP(8, lcdc, dsub, _, _, _, _, _),
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dlcdc.h61 * LCDC register constants.
117 void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
118 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
119 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
123 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
/openbmc/linux/Documentation/fb/
H A Dsh7760fb.rst2 SH7760/SH7763 integrated LCDC Framebuffer driver
7 The SH7760/SH7763 have an integrated LCD Display controller (LCDC) which
48 The LCDC must explicitly be told about the type of LCD panel
126 .name = "sh7760-lcdc",
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dmdp4.yaml46 description: LCDC/LVDS
60 qcom,lcdc-align-lsb:
63 Indication that LSB alignment should be used for LCDC.
/openbmc/linux/arch/sh/boards/mach-se/7722/
H A Dsetup.c160 /* LCDC I/O */ in se7722_setup()
168 /* LCDC */ in se7722_setup()
173 __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */ in se7722_setup()
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3288_vop.c39 /* lcdc(vop) iodomain select 1.8V */ in rk3288_set_io_vsel()
62 /* Set the LCDC(vop) iodomain to 1.8V */ in rk3288_vop_probe()
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c27 USB, LCDC, enumerator
56 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
90 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
111 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,

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