1*ab42b818SMauro Carvalho Chehab================================================ 2*ab42b818SMauro Carvalho ChehabSH7760/SH7763 integrated LCDC Framebuffer driver 3*ab42b818SMauro Carvalho Chehab================================================ 4*ab42b818SMauro Carvalho Chehab 5*ab42b818SMauro Carvalho Chehab0. Overview 6*ab42b818SMauro Carvalho Chehab----------- 7*ab42b818SMauro Carvalho ChehabThe SH7760/SH7763 have an integrated LCD Display controller (LCDC) which 8*ab42b818SMauro Carvalho Chehabsupports (in theory) resolutions ranging from 1x1 to 1024x1024, 9*ab42b818SMauro Carvalho Chehabwith color depths ranging from 1 to 16 bits, on STN, DSTN and TFT Panels. 10*ab42b818SMauro Carvalho Chehab 11*ab42b818SMauro Carvalho ChehabCaveats: 12*ab42b818SMauro Carvalho Chehab 13*ab42b818SMauro Carvalho Chehab* Framebuffer memory must be a large chunk allocated at the top 14*ab42b818SMauro Carvalho Chehab of Area3 (HW requirement). Because of this requirement you should NOT 15*ab42b818SMauro Carvalho Chehab make the driver a module since at runtime it may become impossible to 16*ab42b818SMauro Carvalho Chehab get a large enough contiguous chunk of memory. 17*ab42b818SMauro Carvalho Chehab 18*ab42b818SMauro Carvalho Chehab* The driver does not support changing resolution while loaded 19*ab42b818SMauro Carvalho Chehab (displays aren't hotpluggable anyway) 20*ab42b818SMauro Carvalho Chehab 21*ab42b818SMauro Carvalho Chehab* Heavy flickering may be observed 22*ab42b818SMauro Carvalho Chehab a) if you're using 15/16bit color modes at >= 640x480 px resolutions, 23*ab42b818SMauro Carvalho Chehab b) during PCMCIA (or any other slow bus) activity. 24*ab42b818SMauro Carvalho Chehab 25*ab42b818SMauro Carvalho Chehab* Rotation works only 90degress clockwise, and only if horizontal 26*ab42b818SMauro Carvalho Chehab resolution is <= 320 pixels. 27*ab42b818SMauro Carvalho Chehab 28*ab42b818SMauro Carvalho ChehabFiles: 29*ab42b818SMauro Carvalho Chehab - drivers/video/sh7760fb.c 30*ab42b818SMauro Carvalho Chehab - include/asm-sh/sh7760fb.h 31*ab42b818SMauro Carvalho Chehab - Documentation/fb/sh7760fb.rst 32*ab42b818SMauro Carvalho Chehab 33*ab42b818SMauro Carvalho Chehab1. Platform setup 34*ab42b818SMauro Carvalho Chehab----------------- 35*ab42b818SMauro Carvalho ChehabSH7760: 36*ab42b818SMauro Carvalho Chehab Video data is fetched via the DMABRG DMA engine, so you have to 37*ab42b818SMauro Carvalho Chehab configure the SH DMAC for DMABRG mode (write 0x94808080 to the 38*ab42b818SMauro Carvalho Chehab DMARSRA register somewhere at boot). 39*ab42b818SMauro Carvalho Chehab 40*ab42b818SMauro Carvalho Chehab PFC registers PCCR and PCDR must be set to peripheral mode. 41*ab42b818SMauro Carvalho Chehab (write zeros to both). 42*ab42b818SMauro Carvalho Chehab 43*ab42b818SMauro Carvalho ChehabThe driver does NOT do the above for you since board setup is, well, job 44*ab42b818SMauro Carvalho Chehabof the board setup code. 45*ab42b818SMauro Carvalho Chehab 46*ab42b818SMauro Carvalho Chehab2. Panel definitions 47*ab42b818SMauro Carvalho Chehab-------------------- 48*ab42b818SMauro Carvalho ChehabThe LCDC must explicitly be told about the type of LCD panel 49*ab42b818SMauro Carvalho Chehabattached. Data must be wrapped in a "struct sh7760fb_platdata" and 50*ab42b818SMauro Carvalho Chehabpassed to the driver as platform_data. 51*ab42b818SMauro Carvalho Chehab 52*ab42b818SMauro Carvalho ChehabSuggest you take a closer look at the SH7760 Manual, Section 30. 53*ab42b818SMauro Carvalho Chehab(http://documentation.renesas.com/eng/products/mpumcu/e602291_sh7760.pdf) 54*ab42b818SMauro Carvalho Chehab 55*ab42b818SMauro Carvalho ChehabThe following code illustrates what needs to be done to 56*ab42b818SMauro Carvalho Chehabget the framebuffer working on a 640x480 TFT:: 57*ab42b818SMauro Carvalho Chehab 58*ab42b818SMauro Carvalho Chehab #include <linux/fb.h> 59*ab42b818SMauro Carvalho Chehab #include <asm/sh7760fb.h> 60*ab42b818SMauro Carvalho Chehab 61*ab42b818SMauro Carvalho Chehab /* 62*ab42b818SMauro Carvalho Chehab * NEC NL6440bc26-01 640x480 TFT 63*ab42b818SMauro Carvalho Chehab * dotclock 25175 kHz 64*ab42b818SMauro Carvalho Chehab * Xres 640 Yres 480 65*ab42b818SMauro Carvalho Chehab * Htotal 800 Vtotal 525 66*ab42b818SMauro Carvalho Chehab * HsynStart 656 VsynStart 490 67*ab42b818SMauro Carvalho Chehab * HsynLenn 30 VsynLenn 2 68*ab42b818SMauro Carvalho Chehab * 69*ab42b818SMauro Carvalho Chehab * The linux framebuffer layer does not use the syncstart/synclen 70*ab42b818SMauro Carvalho Chehab * values but right/left/upper/lower margin values. The comments 71*ab42b818SMauro Carvalho Chehab * for the x_margin explain how to calculate those from given 72*ab42b818SMauro Carvalho Chehab * panel sync timings. 73*ab42b818SMauro Carvalho Chehab */ 74*ab42b818SMauro Carvalho Chehab static struct fb_videomode nl6448bc26 = { 75*ab42b818SMauro Carvalho Chehab .name = "NL6448BC26", 76*ab42b818SMauro Carvalho Chehab .refresh = 60, 77*ab42b818SMauro Carvalho Chehab .xres = 640, 78*ab42b818SMauro Carvalho Chehab .yres = 480, 79*ab42b818SMauro Carvalho Chehab .pixclock = 39683, /* in picoseconds! */ 80*ab42b818SMauro Carvalho Chehab .hsync_len = 30, 81*ab42b818SMauro Carvalho Chehab .vsync_len = 2, 82*ab42b818SMauro Carvalho Chehab .left_margin = 114, /* HTOT - (HSYNSLEN + HSYNSTART) */ 83*ab42b818SMauro Carvalho Chehab .right_margin = 16, /* HSYNSTART - XRES */ 84*ab42b818SMauro Carvalho Chehab .upper_margin = 33, /* VTOT - (VSYNLEN + VSYNSTART) */ 85*ab42b818SMauro Carvalho Chehab .lower_margin = 10, /* VSYNSTART - YRES */ 86*ab42b818SMauro Carvalho Chehab .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 87*ab42b818SMauro Carvalho Chehab .vmode = FB_VMODE_NONINTERLACED, 88*ab42b818SMauro Carvalho Chehab .flag = 0, 89*ab42b818SMauro Carvalho Chehab }; 90*ab42b818SMauro Carvalho Chehab 91*ab42b818SMauro Carvalho Chehab static struct sh7760fb_platdata sh7760fb_nl6448 = { 92*ab42b818SMauro Carvalho Chehab .def_mode = &nl6448bc26, 93*ab42b818SMauro Carvalho Chehab .ldmtr = LDMTR_TFT_COLOR_16, /* 16bit TFT panel */ 94*ab42b818SMauro Carvalho Chehab .lddfr = LDDFR_8BPP, /* we want 8bit output */ 95*ab42b818SMauro Carvalho Chehab .ldpmmr = 0x0070, 96*ab42b818SMauro Carvalho Chehab .ldpspr = 0x0500, 97*ab42b818SMauro Carvalho Chehab .ldaclnr = 0, 98*ab42b818SMauro Carvalho Chehab .ldickr = LDICKR_CLKSRC(LCDC_CLKSRC_EXTERNAL) | 99*ab42b818SMauro Carvalho Chehab LDICKR_CLKDIV(1), 100*ab42b818SMauro Carvalho Chehab .rotate = 0, 101*ab42b818SMauro Carvalho Chehab .novsync = 1, 102*ab42b818SMauro Carvalho Chehab .blank = NULL, 103*ab42b818SMauro Carvalho Chehab }; 104*ab42b818SMauro Carvalho Chehab 105*ab42b818SMauro Carvalho Chehab /* SH7760: 106*ab42b818SMauro Carvalho Chehab * 0xFE300800: 256 * 4byte xRGB palette ram 107*ab42b818SMauro Carvalho Chehab * 0xFE300C00: 42 bytes ctrl registers 108*ab42b818SMauro Carvalho Chehab */ 109*ab42b818SMauro Carvalho Chehab static struct resource sh7760_lcdc_res[] = { 110*ab42b818SMauro Carvalho Chehab [0] = { 111*ab42b818SMauro Carvalho Chehab .start = 0xFE300800, 112*ab42b818SMauro Carvalho Chehab .end = 0xFE300CFF, 113*ab42b818SMauro Carvalho Chehab .flags = IORESOURCE_MEM, 114*ab42b818SMauro Carvalho Chehab }, 115*ab42b818SMauro Carvalho Chehab [1] = { 116*ab42b818SMauro Carvalho Chehab .start = 65, 117*ab42b818SMauro Carvalho Chehab .end = 65, 118*ab42b818SMauro Carvalho Chehab .flags = IORESOURCE_IRQ, 119*ab42b818SMauro Carvalho Chehab }, 120*ab42b818SMauro Carvalho Chehab }; 121*ab42b818SMauro Carvalho Chehab 122*ab42b818SMauro Carvalho Chehab static struct platform_device sh7760_lcdc_dev = { 123*ab42b818SMauro Carvalho Chehab .dev = { 124*ab42b818SMauro Carvalho Chehab .platform_data = &sh7760fb_nl6448, 125*ab42b818SMauro Carvalho Chehab }, 126*ab42b818SMauro Carvalho Chehab .name = "sh7760-lcdc", 127*ab42b818SMauro Carvalho Chehab .id = -1, 128*ab42b818SMauro Carvalho Chehab .resource = sh7760_lcdc_res, 129*ab42b818SMauro Carvalho Chehab .num_resources = ARRAY_SIZE(sh7760_lcdc_res), 130*ab42b818SMauro Carvalho Chehab }; 131